Electromagnetic compatibility design considerations for multi-layer PCB board design

Electromagnetic Compatibility (EMC) is an emerging comprehensive discipline that mainly studies electromagnetic interference and anti-interference issues. Electromagnetic compatibility means that electronic equipment or systems do not reduce their performance indicators due to electromagnetic interference under specified electromagnetic environment levels. At the same time, the electromagnetic radiation they generate does not exceed the limited limit level and does not affect the normal operation of other systems. And achieve the purpose of non-interference between equipment and equipment and systems and systems, and working together reliably. Electromagnetic interference (EMI) is caused by electromagnetic interference sources transferring energy to sensitive systems through coupling paths. It includes three basic forms: conduction by wires and public ground wires, space radiation, or near-field coupling. Practice has proved that even if the circuit schematic is designed correctly and the printed circuit board is improperly designed, it will have an adverse impact on the reliability of electronic equipment. Therefore, ensuring the electromagnetic compatibility of the printed circuit board is the key to the entire system design. This article mainly discusses electromagnetic compatibility. Technology and its application in multi-layer printed circuit board (PCB) design.

PCB is the support for circuit components and devices in electronic products. It provides electrical connections between circuit components and devices and is the most basic component of various electronic equipment. Nowadays, large-scale and very large-scale integrated circuits have been widely used in electronic equipment, and the mounting density of components on printed circuit boards is getting higher and higher, and the signal transmission speed is getting faster and faster, which has caused EMC issues are also becoming more and more prominent. PCBs are divided into single-sided boards (single-layer boards), double-sided boards (double-layer boards) and multi-layer boards. Single-sided and double-sided boards are generally used for low- and medium-density wiring circuits and low-integration circuits, while multi-layer boards use high-density wiring and highly integrated circuits. From the perspective of electromagnetic compatibility, single-sided and double-sided panels are not suitable for high-speed circuits. Single-sided and double-sided wiring can no longer meet the requirements of high-performance circuits. The development of multi-layer wiring circuits provides a possibility to solve the above problems, and its Applications are becoming more and more widespread.


1. Characteristics of multi-layer wiring

PCB is composed of organic and inorganic dielectric materials with a multi-layer structure. The connection between layers is realized through via holes. The via holes are plated or filled with metal materials to achieve electrical signal conduction between layers. The reason why multi-layer wiring is widely used has the following characteristics:

(1) There are dedicated power layers and ground layers inside the multi-layer board. The power layer can serve as a noise loop to reduce interference; at the same time, the power layer also provides a loop for all signals in the system to eliminate common impedance coupling interference. The impedance of the power supply line is reduced, thereby reducing public impedance interference.

(2) Multilayer boards use a special ground layer, and there are special ground wires for all signal lines. Characteristics of the signal line: The impedance is stable and easy to match, which reduces waveform distortion caused by reflection; at the same time, the use of a special ground layer increases the distributed capacitance between the signal line and the ground line, reducing crosstalk.

2. Layer design of printed circuit boards

(1) PCB wiring rules

The electromagnetic compatibility analysis of multi-layer circuit boards can be based on Kirchhoff’s law and Faraday’s law of electromagnetic induction. According to Kirchhoff’s law, the transmission of any time domain signal from source to load must have a path with the lowest impedance.

PCBs with multiple layers are often used in high-speed, high-performance systems, with multiple layers used for direct current (DC) power or ground reference planes. These planes are usually solid planes without any separation because there are enough layers to serve as power or ground planes so there is no need to put different DC voltages on the same layer. This layer will serve as a current return path for signals on the transmission lines adjacent to them. Constructing a low-impedance current return path is the most important EMC goal of these planar layers.

The signal layer is distributed between the physical reference plane layers. They can be symmetrical striplines and asymmetrical striplines. Take a 12-layer board as an example to illustrate the structure and layout of a multi-layer board. Its layered structure is T – P – S – P – S – P – S – P – S – S – P – B, “T” is the top layer, “P” is the reference plane layer, and “S” is the signal layer. “B” is the bottom layer. From the top to the bottom, they are layer 1, layer 2,? ? Level 12. The top and bottom layers are used as pads for components, and signals should not travel too long on the top and bottom layers to reduce direct radiation from traces. Incompatible signal lines should be isolated from each other to avoid coupling interference between each other. High frequency and low frequency, large current and small current, digital and analog signal lines are incompatible. In the component layout, incompatible components should be placed in different positions on the printed board. The layout of the signal lines should still be Be careful to isolate them. Please pay attention to the following three issues when designing:

(2) Determine which reference plane layer will contain multiple power regions for different DC voltages. Assuming multiple DC voltages on layer 11, it means that the designer must keep high-speed signals as far away from layer 10 and the bottom layer as possible, because return current cannot flow through the reference plane above layer 10, and stitching capacitors need to be used, layer 3 , 5, 7 and 9 layers are the signal layers of high-speed signals respectively. The traces of important signals should be laid out in one direction as much as possible to optimize the number of possible trace channels on the layer. Signal traces distributed on different layers should be perpendicular to each other, which can reduce the coupling interference of electric fields and magnetic fields between the lines. The 3rd and 7th layers can be set as “east-west” traces, while the 5th and 9th layers are set Route the wires “North and South”. Which layer the traces are laid on depends on the direction in which they reach their destination.

(3) Layer changes during high-speed signal routing, and which different layers are used for an independent routing, ensure that the return current flows from one reference plane to the required new reference plane. This is to reduce the signal loop area and reduce the differential mode current radiation and common mode current radiation of the loop. Loop radiation is proportional to current intensity and loop area. In fact, the best designs do not require the return current to change the reference plane, but simply change from one side of the reference plane to the other. For example, combinations of signal layers can be used as signal layer pairs: layer 3 and layer 5, layer 5 and layer 7, layer 7 and layer 9, which allows an east-west and north-south direction to form a wiring combination. But the combination of layers 3 and 9 should not be used because this requires return current to flow from layer 4 to layer 8. Although a decoupling capacitor can be placed near the via, at high frequencies the presence of lead and via inductance renders the capacitor useless. Moreover, this kind of wiring will increase the signal loop area, which is detrimental to reducing current radiation.

(4) Select the DC voltage for the reference plane layer. In this example, due to the high speed of signal processing inside the processor, there is a lot of noise on the power/ground reference pins. Therefore, it is important to use decoupling capacitors on supplying the same DC voltage to the processor, and to use decoupling capacitors as efficiently as possible. The best way to reduce the inductance of these components is to keep the connecting traces as short and wide as possible, and to keep the vias as short and thick as possible.

If layer 2 is assigned as “ground” and layer 4 is assigned as power to the processor, the vias should be as short as possible from the top layer where the processor and decoupling capacitors are placed. The remaining portion of the air that extends to the bottom layer of the board does not contain any significant current and will not act as an antenna due to the short distance. Table 1 lists reference configurations for stackup design layouts.

3. Reference configuration of stacked design layout

(1)20-H Rule and 3-W Rule

In the electromagnetic compatibility design of multi-layer PCB boards, there are two basic principles for determining the distance between the power layer and the edge of the multi-layer board and solving the distance between printed strips: the 20-H rule and the 3-W rule.

(2) – H principle: Due to the connection between magnetic fluxes, RF current usually exists at the edge of the power plane. This inter-layer coupling is called edge effect. When using high-speed digital logic and clock signals, the power planes RF currents will couple to each other, as shown in Figure 1. In order to reduce this effect, the physical size of the power plane should be at least 20H smaller than the physical size closest to the ground plane (H is the distance between the power plane and the ground plane). The edge effect of the power supply usually occurs around 10H, 20H When about 10% of the magnetic flux is blocked, if you want to achieve 98% of the magnetic flux being blocked, you need a boundary value of 100%, as shown in Figure 1. The 20-H rule determines the physical distance between the power plane and the nearest ground plane. This distance includes copper thickness, prefill, and insulation separation layers. Using 20-H can increase the resonant frequency of the PCB itself.

RF edge effect of PCB

(3) – W rule: When the distance between two printed lines is small, electromagnetic crosstalk will occur between the two lines, which will cause the relevant circuits to malfunction. To avoid this interference, the distance between any lines should be kept not less than 3 times The width of printed lines is not less than 3W (W is the width of printed lines). The width of printed lines depends on the line impedance requirements. Too wide will affect the wiring density, and too narrow will affect the integrity and strength of the signal transmitted to the terminal. The wiring of clock circuits, differential pairs, and I/O ports are all basic applications of the 3-W principle. 3 – The W principle only represents the boundary of the electromagnetic flux line where the crosstalk energy is attenuated by 70%. If the requirements are higher, such as ensuring the electromagnetic flux boundary line where the crosstalk energy is attenuated by 98%, a 10W interval must be adopted.

4. Ground wire layout

First of all, it is necessary to establish the concept of distributed parameters. Above a certain frequency, any metal wire must be regarded as a device composed of resistance and inductance. Therefore, the ground lead has a certain impedance and forms an electrical loop. Whether it is single-point grounding or multi-point grounding, it must form a low-impedance loop into the real ground or rack. A typical printed trace of 25mm length will exhibit approximately 15 to 20nH inductance. Coupled with the presence of distributed capacitance, a resonant circuit will be formed between the ground plate and the equipment rack. Secondly, when ground current flows through the ground wire, transmission line effect and antenna effect will occur. When the length of the line is 1/4 wavelength, it shows a high impedance, and the ground line is actually an open circuit. Instead, the ground line becomes an antenna that radiates outward. Finally, the ground plate is filled with eddy currents formed by high-frequency currents and disturbances. Therefore, many loops are formed between ground points. The diameter of these loops (or distance between ground points) should be less than 1/20 of the highest frequency wavelength. Choose the appropriate device It is an important factor for the success of the design. Especially when selecting logic devices, try to choose a logic device with a rise time longer than 5ns. Never choose a logic device with a timing that is faster than the circuit requirements.

5. Arrangement of power cords

For multi-layer boards, the power layer-ground layer structure is used for power supply. The characteristic impedance of this structure is much smaller than the rail pair and can be less than 1Ω. This structure has a certain capacitance, and there is no need to add high-frequency decoupling capacitors next to each integrated chip. Even if the layer capacitor capacity is not enough and an external decoupling capacitor is needed, it should not be added next to the integrated chip. It can be added anywhere on the printed board. The power pins and ground pins of the integrated chip can be directly connected to the power layer and ground layer through metalized through holes, so the power supply loop is always minimal. Due to the principle that “current always takes the path with the smallest impedance”, the high-frequency return flow on the ground layer always runs close to the track, unless there is a ground gap blocking it, so the signal loop is always the smallest. It can be seen that compared with the rail pair power supply, the power layer-ground layer structure has the advantages of simple and flexible layout and good electromagnetic compatibility.


In short, in multi-layer PCB design, components should be placed in groups to prevent inter-group interference; high-speed circuits should be positioned appropriately to avoid interference with other circuits through electric field coupling or magnetic field coupling; ground wires should be set separately according to the situation to prevent common interference. Ground wire impedance coupling interference; the area of the power supply loop should be reduced to a minimum, and the power supply loops of different power supplies should not overlap to avoid magnetic field coupling; incompatible signal lines should be isolated from each other to avoid coupling interference; it should also be Reduce the signal loop area to reduce loop radiation and common mode radiation.


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