Controllability and electromagnetic compatibility design of high-speed PCB

following aspects:

(1) Whether the distance between wires and wires, wires and component pads, wires and through holes, component pads and through holes, and through holes and through holes is reasonable and meets production requirements.
(2) Are the widths of the power and ground wires appropriate, and are the power and ground wires tightly coupled (low wave impedance)? Is there any place in the PCB where the ground wire can be widened?
(3) Whether the best measures have been taken for key signal lines, such as keeping them to the shortest length, adding protective lines, and clearly separating input lines and output lines.
(4) Whether the analog circuit and digital circuit parts have independent ground wires.
(5) Whether graphics (such as icons, labels) added to the PCB later will cause signal short circuits.
(6) Modify some unideal line shapes.
(7) Are there process lines added to the PCB? Whether the solder resist meets the requirements of the production process, whether the solder resist size is appropriate, and whether the character mark is pressed on the device pad to avoid affecting the quality of the electrical assembly.
(8) Whether the edge of the outer frame of the power supply ground layer in the multilayer board is reduced. If the copper foil of the power supply ground layer is exposed outside the board, it may easily cause a short circuit.

Part 2 PCB Layout

In design, layout is an important link. The quality of the layout results will directly affect the wiring effect, so it can be considered that reasonable layout is the first step to successful PCB design.

There are two layout methods, one is interactive layout and the other is automatic layout. Generally, interactive layout is used to adjust the layout based on automatic layout. During layout, the gate circuit can also be restructured according to the wiring situation. Assignment, swapping the two gates to make it the best layout for easy routing. After the layout is completed, the design files and related information can also be returned and annotated on the schematic diagram, so that the relevant information in the PCB board is consistent with the schematic diagram, so that future filings and design changes can be synchronized, and at the same time, the simulated Information is updated to enable board-level verification of the circuit’s electrical performance and functionality.

1 Consider overall aesthetics

Whether a product is successful or not, one must pay attention to the internal quality, and the other is to take into account the overall beauty. Only when both are perfect can the product be considered successful. On a PCB board, the layout of components must be balanced, dense and orderly, and cannot be top-heavy or heavy.

2 Check the layout

Does the size of the printed board match the size of the processing drawing? Can it meet PCB manufacturing process requirements? Are there any location markers?
Are there any conflicts between components in two-dimensional and three-dimensional space?
Is the component layout dense and orderly, arranged neatly? Have they all been laid out?
Can components that need to be replaced easily be replaced? Is it convenient to plug the plug-in board into the device?
Is there an appropriate distance between the thermal element and the heating element?
Is it easy to adjust the adjustable elements?
Are there any radiators installed where heat dissipation is required? Is the air flow clear?
Is the signal flow smooth with minimal interconnections?
Are plugs, sockets, etc. inconsistent with the mechanical design?
Have you considered the line interference problem?


Part 3 High-speed PCB Design

(1) Challenges faced by electronic system design

With the large-scale increase in the complexity and integration of system design, electronic system designers are engaged in circuit design above 100MHZ, and the operating frequency of the bus has reached or exceeded 50MHZ, and some even exceeded 100MHZ. Currently, about 50% of designs have clock frequencies exceeding 50MHz, and nearly 20% have clock frequencies exceeding 120MHz.

When the system operates at 50MHz, transmission line effects and signal integrity problems will occur; and when the system clock reaches 120MHz, PCBs designed based on traditional methods will not work unless high-speed circuit design knowledge is used. Therefore, high-speed circuit design technology has become a must-have design method for electronic system designers. Controllability of the design process can only be achieved by using the design techniques of high-speed circuit designers.

(2) What is a high-speed circuit?

It is generally believed that if the frequency of a digital logic circuit reaches or exceeds 45MHZ~50MHZ, and the circuits working above this frequency have accounted for a certain amount of the entire electronic system (for example, 1/3), it is called a high-speed circuit.

In fact, the harmonic frequency of the signal edge is higher than the frequency of the signal itself. It is the rapidly changing rising and falling edges of the signal (or signal jump) that causes unexpected results in signal transmission. Therefore, it is usually agreed that if the line propagation delay is greater than 1/2 the rise time of the digital signal driver end, such signals are considered to be high-speed signals and produce transmission line effects.

Signal transmission occurs at the instant when the signal state changes, such as rise or fall time. The signal passes through a fixed period of time from the driving end to the receiving end. If the transmission time is less than 1/2 of the rise or fall time, then the reflected signal from the receiving end will reach the driving end before the signal changes state. Conversely, the reflected signal will arrive at the driver after the signal has changed state. If the reflected signal is strong, the superimposed waveform may change the logic state.

(3) Determination of high-speed signals

Above we have defined the prerequisites for the transmission line effect to occur, but how do we know whether the line delay is greater than 1/2 the signal rise time at the driver end? Generally, the typical value of the signal rise time can be given by the device manual, while the signal propagation time is determined by the actual wiring length in PCB design. The figure below shows the corresponding relationship between the signal rise time and the allowed wiring length (delay). ​

The delay per inch on the PCB board is 0.167ns. However, if there are many vias, many device pins, and many constraints set on the network line, the delay will increase. Usually the signal rise time of high-speed logic devices is about 0.2ns. If there is a GaAs chip on the board, the maximum wiring length is 7.62mm.

Let Tr be the signal rise time, and Tpd be the signal line propagation delay. If Tr≥4Tpd, the signal falls in the safe area. If 2Tpd≥Tr≥4Tpd, the signal falls in the uncertainty area. If Tr≤2Tpd, the signal falls in the problem area. For signals that fall into uncertain and problem areas, high-speed routing methods should be used.

(4) What is a transmission line?

The traces on the PCB board can be equivalent to the series and parallel capacitors, resistors and inductors shown in the figure below. The typical value of the series resistor is 0.25-0.55 ohms/foot, and the parallel resistor value is usually very high due to the insulation layer. After adding parasitic resistance, capacitance and inductance to the actual PCB connection, the final impedance on the connection is called the characteristic impedance Zo. The wider the wire diameter, the closer it is to power/ground, or the higher the dielectric constant of the isolation layer, the smaller the characteristic impedance. If the impedance of the transmission line and the receiving end does not match, the output current signal and the final stable state of the signal will be different, which will cause the signal to be reflected at the receiving end. This reflected signal will be transmitted back to the signal transmitting end and reflected back again. As the energy decreases, the amplitude of the reflected signal will decrease until the signal’s voltage and current stabilize. This effect is called oscillation, and oscillations in a signal are often seen on the rising and falling edges of the signal.

(5) Transmission line effect

Based on the transmission line model defined above, in summary, the transmission line will bring the following effects to the entire circuit design.

5.1 Reflected signal

If a trace is not properly terminated (terminated), the signal pulse from the driver is reflected at the receiver, causing unintended effects and distorting the signal profile. When the distortion deformation is very significant, it can lead to various errors and cause design failure. At the same time, the sensitivity of the distorted signal to noise increases, which can also cause design failure. If the above conditions are not adequately considered, EMI will increase significantly, which will not only affect the design results, but also cause the failure of the entire system. The main causes of reflected signals are: excessively long traces; unmatched terminated transmission lines, excessive capacitance or inductance, and impedance mismatch.

5.2 Delay and timing errors

Signal delays and timing errors manifest themselves as: when the signal changes between the high and low logic level thresholds, the signal does not transition for a period of time. Excessive signal delays can lead to timing errors and confusion in device functionality. Problems usually arise when there are multiple sinks. The circuit designer must determine the worst-case time delay to ensure the correctness of the design. Reasons for signal delay: driver overload and traces that are too long.

5.3 Multiple logic level threshold crossing errors

A signal may cross a logic level threshold multiple times during a transition, causing this type of error. The error of crossing the logic level threshold multiple times is a special form of signal oscillation, that is, the oscillation of the signal occurs near the logic level threshold. Crossing the logic level threshold multiple times will lead to logic dysfunction. Causes of reflected signals: too long traces, unterminated transmission lines, excessive capacitance,Or inductance and impedance mismatch.

5.4 Overshoot and undershoot

Overshoot and undershoot come from two reasons: the trace is too long or the signal changes too fast. Although most components are protected by input protection diodes at the receiving end, sometimes these overshoot levels can far exceed the component’s supply voltage range and damage the component.

5.5 Crosstalk

Crosstalk shows that when a signal passes through a signal line, related signals will be induced on the adjacent signal line on the PCB board, which we call crosstalk. The closer the signal line is to the ground line and the larger the line spacing, the smaller the crosstalk signal generated. Asynchronous signals and clock signals are more prone to crosstalk. Therefore, the method to eliminate crosstalk is to remove the signal where crosstalk occurs or shield the signal that is seriously interfered with.

5.6 Electromagnetic radiation

EMI (Electro-Magnetic Interference) refers to electromagnetic interference. The problems caused include excessive electromagnetic radiation and sensitivity to electromagnetic radiation. EMI manifests itself in the fact that when a digital system is powered on and running, it radiates electromagnetic waves to the surrounding environment, thus interfering with the normal operation of electronic equipment in the surrounding environment. The main reasons are that the circuit operating frequency is too high and the layout and wiring are unreasonable. There are currently software tools for EMI simulation, but EMI simulators are expensive, and it is difficult to set simulation parameters and boundary conditions, which will directly affect the accuracy and practicality of the simulation results. The most common approach is to apply various design rules for controlling EMI in every aspect of the design to achieve rule-driven and control in each aspect of the design.

(6) Methods to avoid transmission line effects

In view of the impacts caused by the above-mentioned transmission line problems, we talk about methods to control these impacts from the following aspects.

6.1 Strictly control the length of key network cables

If there are high-speed transition edges in the design, the transmission line effect on the PCB must be considered. The fast integrated circuit chips with very high clock frequencies now commonly used have such problems. There are some basic principles to solve this problem: If designing with CMOS or TTL circuits, the operating frequency is less than 10MHz, and the wiring length should be no more than 7 inches. At an operating frequency of 50MHz, the wiring length should be no more than 1.5 inches. If the operating frequency reaches or exceeds 75MHz, the wiring length should be within 1 inch. The maximum wiring length for GaAs chips should be 0.3 inches. If it exceeds this standard, there is a problem with the transmission line.

6.2 Properly plan the topology of the wiring

Another way to address transmission line effects is to choose the correct routing path and termination topology. The wiring topology refers to the wiring sequence and wiring structure of a network cable. When using high-speed logic devices, signals with rapidly changing edges will be distorted by branch traces on the signal trunk unless trace branch lengths are kept short. Under normal circumstances, PCB wiring adopts two basic topologies, namely daisy chain wiring and star distribution.

For daisy chain wiring, the wiring starts at the driving end and goes to each receiving end. If a series resistor is used to change signal characteristics, the series resistor should be placed close to the driver end. Daisy chain wiring works best in controlling high-order harmonic interference from wiring. However, this wiring method has the lowest routing rate and is not easy to 100% routing. In actual design, we make the branch length in daisy chain wiring as short as possible. The safe length value should be: Stub Delay <= Trt *0.1.

For example, the branch end length in high-speed TTL circuits should be less than 1.5 inches. This topology takes up less routing space and can be terminated with a single resistor match. However, this wiring structure makes the reception of signals at different signal receiving ends asynchronous.

The star topology can effectively avoid the problem of clock signal desynchronization, but it is very difficult to manually complete wiring on a high-density PCB. Using an automatic router is the best way to complete star wiring. Terminating resistors are required on each branch. The resistance of the terminating resistor should match the characteristic impedance of the connection. This can be calculated manually or through CAD tools to calculate the characteristic impedance value and terminal matching resistance value. ​

In the above two examples, simple termination resistors are used. In practice, more complex matching terminations can be used. The first option is RC matching termination. RC matching terminals can reduce power consumption, but can only be used when the signal operation is relatively stable. This method is most suitable for matching clock line signals. The disadvantage is that the capacitance in the RC matching terminal may affect the shape and propagation speed of the signal.

Series resistor matching terminations do not consume additional power but will slow down signal transmission. This method is used for bus driver circuits where time delay has little impact. Series resistor matching terminations also have the advantage of reducing the number of components on the board and the wiring density.

The last method is to separate the matching terminal. In this method, the matching component needs to be placed near the receiving end. The advantage is that it will not lower the signal and can avoid noise very well. Typically used for TTL input signals (ACT, HCT, FAST).

In addition, the packaging type and installation type of the terminal matching resistor must also be considered. Generally SMD surface mount resistors have lower inductance than through-hole components, so SMD packaged components become the first choice. If you choose an ordinary plug-in resistor, there are two installation methods available: vertical and horizontal.

In the vertical installation method, one installation pin of the resistor is very short, which can reduce the thermal resistance between the resistor and the circuit board, making it easier for the heat of the resistor to dissipate into the air. But longer vertical installations increase the resistor’s inductance. Horizontal installation has lower inductance due to lower installation. However, overheated resistors will drift, and in the worst case, the resistors become open circuits, causing PCB trace termination matching failure and becoming a potential failure factor.

6.3 Methods to suppress electromagnetic interference

Solving signal integrity issues well will improve the electromagnetic compatibility (EMC) of the PCB board. One of the most important things is to ensure that the PCB board is well grounded. For complex designs, using one signal layer and one ground layer is a very effective method. In addition, minimizing the signal density on the outermost layer of the circuit board is also a good way to reduce electromagnetic radiation. This method can be achieved by using the “surface layer” technology “Build-up” to design and manufacture PCBs. The surface area layer is achieved by adding a combination of thin insulating layers and micropores for penetrating these layers on ordinary process PCBs. Resistors and capacitors can be buried under the surface layer, and the trace density per unit area will nearly double, so it can Reduce PCB size. The reduction in PCB area has a huge impact on the topology of the traces, which means reduced current loops and reduced branch trace lengths, and electromagnetic radiation is approximately proportional to the area of the current loop; at the same time, the small volume feature means high-density wiring Pin-encapsulated devices can be used, which in turn reduces the wiring length, thereby reducing the current loop and improving electromagnetic compatibility characteristics.

6.4 Other possible technologies

To reduce transient overshoot of the voltage on the integrated circuit chip power supply, decoupling capacitors should be added to the integrated circuit chip. This can effectively remove the effects of burrs on the power supply and reduce radiation from the power loop on the printed board.

Decoupling capacitors work best at smoothing glitches when they are connected directly to the power leg of the integrated circuit rather than to the power plane. This is why some device sockets have decoupling capacitors, and some devices require that the distance between the decoupling capacitor and the device be small enough.

Any high-speed and high-power devices should be placed as close together as possible to reduce transient overshoot of the supply voltage.

Without a power plane, long power connections can form loops between signals and circuits, becoming sources of radiation and prone to inductive circuits.

The situation where traces form a loop that does not pass through the same network cable or other traces is called an open loop. If the loop passes through other traces of the same network cable, it forms a closed loop. Antenna effects occur in both cases (wire antennas and loop antennas). The antenna produces EMI radiation to the outside world and is also a sensitive circuit itself. Loop closure is an issue that must be considered because the radiation it produces is approximately proportional to the closed loop area.



High-speed circuit design is a very complex design process. ZUKEN’s high-speed circuit routing algorithm (Route Editor) and EMC/EMI analysis software (INCASES, Hot-Stage) can be used to analyze and find problems. The methods described in this article are specifically designed to solve these high-speed circuit design problems. In addition, there are multiple factors that need to be considered when designing high-speed circuits, and these factors are sometimes in conflict with each other. If high-speed devices are placed close together, although delay can be reduced, crosstalk and significant thermal effects may occur. Therefore, in the design, it is necessary to weigh various factors and make comprehensive compromise considerations to not only meet the design requirements, but also reduce the design complexity. The adoption of high-speed PCB design methods constitutes the controllability of the design process. Only what is controllable can be reliable and successful!

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