PCB routing basics (I): power integrity and PDN design

SI (signal integrity) studies the waveform quality of the signal, while PI (power integrity) studies the waveform quality of the power supply. The object of PI is PDN (Power Distribution Network). It studies power supply problems from a more systematic perspective, eliminates or alleviates power supply noise, meets the load’s demand for currents of different frequencies, and provides clean, stable, and reliable power for the load. Like SI, PI is also one of the basic requirements of PCB engineers. Whether the wiring is good or not, PDN is one of the important assessment directions.

The previous article introduced signal integrity in detail, and this section introduces power integrity.

What is the difference between the two? The analysis basis of SI is the transmission line, while the analysis basis of PI is the transmission plane. The common rectification methods of SI include modifying the routing width, length, and reference layer, while the rectification methods of PI include modifying the routing of the power plane/ground plane, optimizing the matching capacitor value, the number of capacitors, or the installation method.

In the design of mobile phone baseband hardware or other circuit systems, PDN should be the most complex interconnection structure.

I also recommend that novices start with the power supply. The power supply here includes two aspects. The first aspect is the basic power supply structure, including power supply architectures such as BUCK and LDO. The previous article has introduced it in detail. Through the power tree, you can basically understand the power requirements of each module on the mobile phone. Take the power structure in the 5.3 power path chapter of the book “From Device Cognition to Mobile Phone Baseband Circuit Design” as an example, and organize the power tree in the figure below.

Note: The data in the figure is only an example. The actual circuit should be used as the basis.

From the power tree above, a lot of information can be mined. For example, for LDOs that are sensitive to power consumption, only U5 and U6 have good efficiency, and other LDOs have very low efficiency. This requires further optimization of the power supply structure to provide power utilization. There are other information that can be mined, which has been introduced in the previous article and will not be repeated here.

The second aspect is PDN.

PDN can ensure the effectiveness of the entire system and prevent the load from exceeding the voltage fluctuation under complex working conditions, which will cause system abnormalities. Only in this way can the complete design from the power source to the interconnection link and finally to the load be completed. A deep understanding of the power supply will give you a general impression of the overall design of the mobile phone and a deeper understanding of the entire hardware system. In the future, charging, audio, screen camera, and sensor will be much easier.

Of the above two aspects, the former is the focus of power engineers, and the latter is the focus of power integrity engineers. Compared with power engineers, PDN pays more attention to power paths and terminals. The PDN link starts from the power module VRM (voltage regulator model), including PCB traces, capacitors, vias, package and die capacitors on the road. The link is complicated and needs to be analyzed from a systematic perspective. PDN problems and optimized PDN are finally achieved to provide stable and clean power for the chip.

When designing PDN, we focus on both DC and AC.

The DC part is △V=△IR. There is a series resistor from VRM to IC. When DC power is passed, a voltage drop will be generated. For example, if a 1A current passes from VRM to the load and the line resistance is 10mΩ, a voltage drop of 10.01=0.01V will be generated. This voltage drop is often called IR drop. The load current is not a fixed value, but is constantly changing. Therefore, IR drop is also a changing value. For example, when the load is working at 2A, 2*0.01=0.02V will generate a voltage drop of 0.02V, which is very similar to the routing of LDO introduced in the previous article.

However, the load will not work stably at a current value.

For example, when playing games, the CPU will perform various complex calculations and the GPU will perform complex rendering. The switches inside these chips are working at high speed, making the current drawn from the power supply very complex. To analyze this complex time-varying current, resistors cannot be used. It is necessary to introduce parameters related to time and frequency, namely impedance Z (impedance = resistance + capacitive reactance + inductive reactance). The voltage fluctuation is caused by the current fluctuation.

Let’s go back to the classic calculation formula △V=△IR.

Now change it slightly, and it becomes △V=△IZ. R is a constant that has nothing to do with frequency, while Z is related to frequency. △V is the voltage change caused by the change of current. If △V is too large and exceeds the voltage fluctuation allowed by the load, it will be dangerous. Usually, the voltage fluctuation that the load can tolerate is 5% or 3% of the typical value (the specific details are subject to the manual of the actual load), so the voltage fluctuation should avoid exceeding this 5% or 3%. For example, in the figure below, the load requires a voltage of 0.75V. Assuming that the load can tolerate a maximum voltage fluctuation of 3%, that is, the maximum voltage fluctuation that can be accepted is 0.75*0.03=0.0225V, and the actual voltage fluctuation is only 0.015V, which meets the load’s needs.

Let’s look at the formula △V=△I*Z again, and simply transform it to get the following formula

So as long as the PDN impedance Z of our actual circuit is small enough, when Z is small to a certain extent, the voltage fluctuation (△I*Z) caused by current fluctuation will be less than △Vmax, then the impedance at this time is the target impedance Ztarget, so the principle of our PDN design is to optimize the impedance Z on the link to make it lower than the target impedance Ztarget, so as to ensure that the voltage can meet the load requirements. In short, it is to constrain the power supply fluctuation by constraining the impedance. I need to know the target impedance and the specific models of the capacitors on the line capacitors, and accurate simulation is also required to obtain a reliable design.

For example, the figure above is the impedance frequency curve.

If the load has a single operating frequency and only works at a fixed frequency, assuming that the working current is a single-frequency sinusoidal current, then the impedance optimization becomes simple, as long as the impedance of this frequency is lower than the target impedance, but the actual situation is very complicated, and we don’t know the complex specific operating frequency, so for the sake of insurance, we control the impedance within a certain frequency band, rather than the impedance of DC or a single frequency. This seems to be an over-design, but it is indeed a very safe design. The blue curve is our target impedance. What we need to do is to optimize the PDN impedance in this frequency band (within the Feffective frequency) so that the actual red impedance is lower than the target blue impedance within the frequency band required by the load.

The basic concepts and principles of PDN are introduced here. The next section introduces the relevant PDN optimization strategies to guide the actual PCB layout and wiring and the selection and optimization of capacitor components.