The difference between parallel and serial and the system synchronization method of parallel communication

The parallel signals and serial signals referred to in this article include the transmission (communication) method, the interface type, and the protocol characteristics of the data itself, signals, protocols, buses and interfaces. If you want to know the difference between signals, protocols, buses and interfaces, you can read the previous article: [size=1em] A brief history of high-speed serial (I): signals, interfaces, protocols and buses

What are parallel signals? Serial signals?

To understand parallel signals and serial signals, let’s first understand the concepts of parallel communication (transmission) and serial communication (transmission).

Parallel signals are signals that communicate in parallel, while serial signals are signals that communicate in serial. Serial communication refers to the way that data is transmitted in sequence one bit after another on a single one-bit-wide transmission line.

In the early definition, it was also said that there was only one data line and only one bit of data could be sent under each clock pulse; in parallel communication, a byte (8 bits) of data is transmitted from the source to the destination on 8 parallel transmission lines at the same time. It can also be said that there are multiple data lines (how many lines means how many bits), and multiple data bits can be sent under each clock pulse (how many parallel ports send how many bits).

Therefore, the early understanding of serial communication and parallel communication is:

for the same byte of data (8 bits), serial communication must be transmitted one bit at a time from low to high in sequence 8 times, while parallel communication can be transmitted once because there are 8 lines. Figuratively speaking, the line (channel) is compared to a road. If several cars can drive side by side, it can be said to be “parallel”, and if only one car can drive one by one, it belongs to “serial”.

The difference and advantages and disadvantages between parallel communication and serial communication

It is obvious that the speed of parallel communication is much faster than that of serial communication, with higher efficiency and less time-consuming. However, these are all theoretical understandings in the early days when the I/O rate was not high. With the rapid development of information technology, the previous understanding is outdated now, because now is the era of high-speed serial signals (our topic).

In the high-speed state, there is crosstalk between the several data lines of the parallel port, and the parallel port requires signals to be sent and received at the same time, and the delay of any data line will cause problems.

Serial has only one data line, there is no crosstalk between signal lines, and serial can also use low-voltage differential signals, which can greatly improve its anti-interference ability, so it can achieve a higher transmission rate. Although parallel can transmit multiple data bits at a time, the clock is much lower than serial, so serial transmission is currently the first choice for high-speed transmission.

Here, I would like to quote the reply of the die-hard fan “Absolute Zero”:

“For example, in transporting large equipment parts, parallel signals are like multiple trucks, each truck transporting some parts, and everyone can deliver them to the destination within a certain time to assemble the complete equipment. If one truck breaks down, the assembly cannot be completed. Serial signals are like trains. Under normal circumstances, one truck can transport all the parts without any problems.” I think this analogy is quite appropriate. Here, the train itself is faster than the truck.

From another perspective, there are many other ways of parallel transmission, such as system synchronization ([size=1em] common clock) and [size=1.4em] source synchronous clock. Let’s first look at the inherent problems of system synchronization. The following figure is a schematic diagram of the system synchronization method in parallel transmission.

First of all, parallel signals require multi-bit transmission paths, which was acceptable in the early days. However, the phenomenon of Moore’s Law has led to a significant increase in the number of silicon circuits in chips that can be produced compared to decades ago, while the pin density of chip packaging technology has not increased at the same rate as silicon density, so the packaging of I/O pins is actually more expensive than silicon circuits, which means that for most chips, more and more pins are becoming unacceptable.

Just like we all know that the more lanes we have, the faster our traffic efficiency will be, but as urban space becomes smaller and land prices become more expensive, more lanes will slowly become more and more difficult to achieve. Moreover, the I/O rate of parallel itself is not high, just like a tractor or a rough road, if the speed cannot be increased, no matter how many lanes there are, it will be in vain.

The second inherent problem is the timing requirement.

From the above figure, we can see that the data is synchronously launched by chip #1 and captured synchronously by chip #2 using the same clock. The data at the input of chip #2 must meet the setup and hold times relative to the clock input of the chip. The detailed system synchronization timing model is shown in the figure below.

These setup and hold times must be calculated with sufficient margin to allow the clock distribution path delay to the difference between the two chips and through the chip to the launch and capture triggers. The delay may vary depending on chip process, voltage and temperature (PVT) conditions, and margins must be added to account for the worst case. For higher clock frequencies, a phase-locked loop (PLL) may be needed in the chip to adjust the clock phase to compensate for the clock distribution delay within the chip and to accommodate varying process, voltage and temperature conditions. If the clock frequency is high enough, it is impossible to build a system that can reliably transmit data over this common clock bus.