Analysis of parasitic characteristics of PCB vias and key points

In the PCB copying industry, the cost of drilling holes in PCB boards is usually 30% to 40% of the cost of PCB board manufacturing, and vias are one of the important components of multilayer PCBs. In short, every hole on a PCB can be called a via.

Vias appear as discontinuous impedance breakpoints on transmission lines, which will cause signal reflection.

Generally, the equivalent impedance of vias is about 12% lower than that of transmission lines. For example, the impedance of a 50-ohm transmission line will decrease by 6 ohms when passing through a via (specifically related to the size of the via and the thickness of the board, not an absolute reduction).

However, the reflection caused by the impedance discontinuity of vias is actually very small, and its reflection coefficient is only: (44-50)/(44+50)=0.06. The problems caused by vias are more concentrated on the influence of parasitic capacitance and inductance.

The via itself has parasitic stray capacitance

If the diameter of the solder mask area of ​​the via on the ground layer is known to be D2, the diameter of the via pad is D1, the thickness of the PCB is T, and the dielectric constant of the substrate is ε, then the parasitic capacitance of the via is approximately: C=1.41ε. The parasitic capacitance of the via will have the main impact on the circuit by extending the rise time of the signal and reducing the speed of the circuit. For example, for a PCB with a thickness of 50Mil, if the via pad diameter is 20Mil (drilling diameter is 10Mils), and the solder mask diameter is 40Mil, then we can use the above formula to approximate the parasitic capacitance of the via as follows:

The change in rise time caused by this part of the capacitance is approximately:

From these values, it can be seen that although the effect of slowing down the rise delay caused by the parasitic capacitance of a single via is not very obvious, if vias are used multiple times in the routing to switch between layers, multiple vias will be used, and careful consideration should be given during design. In actual design, parasitic capacitance can be reduced by increasing the distance between the via and the copper area (Anti-pad) or reducing the diameter of the pad.

Vias have parasitic capacitance and parasitic inductance.

In the design of high-speed digital circuits, the harm caused by the parasitic inductance of vias is often greater than the influence of parasitic capacitance. Its parasitic series inductance will weaken the contribution of bypass capacitance and weaken the filtering effect of the entire power supply system. We can use the following empirical formula to simply calculate the parasitic inductance of a via:

Where L refers to the inductance of the via, h is the length of the via, and d is the diameter of the center drill hole.

It can be seen from the formula that the diameter of the via has little effect on the inductance, while the length of the via has the greatest impact on the inductance. Still using the above example, the inductance of the via can be calculated as:

If the rise time of the signal is 1ns, then its equivalent impedance is:

XL=πL/T10-90=3.19Ω. Such impedance can no longer be ignored when high-frequency current passes through. In particular, it should be noted that the bypass capacitor needs to pass through two vias when connecting the power layer and the ground layer, so the parasitic inductance of the via will increase exponentially.

Through the above analysis of the parasitic characteristics of vias, we can see that in high-speed PCB design, seemingly simple vias often bring great negative effects to the design of the circuit. In order to reduce the adverse effects of the parasitic effects of vias, the following can be done as much as possible in the design:

． Considering both cost and signal quality, choose a reasonable size of via. If necessary, consider using vias of different sizes.

For example, for vias of power or ground wires, consider using larger sizes to reduce impedance, while for signal routing, use smaller vias. Of course, as the size of the via decreases, the corresponding cost will also increase.

． The two formulas discussed above show that using a thinner PCB board is conducive to reducing the two parasitic parameters of the via.

． Try not to change layers for signal routing on the PCB board, that is, try not to use unnecessary vias.

． The power and ground pins should be drilled nearby vias, and the leads between the vias and the pins should be as short as possible. You can consider drilling multiple vias in parallel to reduce the equivalent inductance.

． Place some grounded vias near the vias where the signal changes layers to provide the closest loop for the signal. You can even place some redundant ground vias on the PCB board.

． For high-speed PCB boards with higher density, you can consider using micro vias.