A brief discussion on EMI solutions in multi-layer PCB design

There are many ways to solve the EMI problem. Modern EMI suppression methods include: using EMI suppression coatings, selecting appropriate EMI suppression components and EMI simulation design, etc. This article starts with the most basic PCB layout and discusses the role and design techniques of PCB layering and stacking in controlling EMI radiation.

Power bus

Reasonably placing capacitors of appropriate capacity near the power pins of the IC can make the IC output voltage jump faster. However, the problem does not end there. Due to the limited frequency response nature of capacitors, they are unable to generate the harmonic power required to cleanly drive the IC output over the full frequency band. In addition, the transient voltage formed on the power bus will form a voltage drop across the inductor of the decoupling path. These transient voltages are the main source of common-mode EMI interference. How should we solve these problems?

As far as the IC on our circuit board is concerned, the power layer around the IC can be regarded as an excellent high-frequency capacitor, which can collect the energy leaked from the discrete capacitors that provide high-frequency energy for clean output. In addition, the inductance of a good power layer should be small, so that the transient signal synthesized by the inductance is also small, thereby reducing common-mode EMI.

Of course, the connection from the power layer to the IC power pin must be as short as possible. Because the rising edge of the digital signal is getting faster and faster, it is best to connect directly to the pad where the IC power pin is located. This needs to be discussed separately.
In order to control common-mode EMI, the power layer must help decoupling and have sufficiently low inductance. This power layer must be a pair of well-designed power layers.

One might ask, how good is good? The answer to this question depends on the layering of the power supply, the materials between the layers, and the operating frequency (which is a function of the IC rise time). Typically, the spacing between power layers is 6 mils, and the interlayer is made of FR4 material, so the equivalent capacitance of the power layer per square inch is about 75 pF. Obviously, the smaller the layer spacing, the greater the capacitance.

There are not many devices with rise times of 100 to 300ps, but according to the current development speed of ICs, devices with rise times in the range of 100 to 300ps will account for a very high proportion. For circuits with rise times of 100 to 300ps, a 3mil layer spacing will no longer be suitable for most applications. At that time, it was necessary to adopt layering technology with a layer spacing of less than 1 mil and replace the FR4 dielectric material with a material with a very high dielectric constant. Today, ceramics and ceramic-based plastics can meet the design requirements for circuits with rise times from 100 to 300 ps.

Although new materials and new methods may be adopted in the future, for today’s common 1 to 3ns rise time circuits, 3 to 6mil layer spacing and FR4 dielectric materials, it is usually sufficient to handle high-end harmonics and keep transient signals low enough. , common mode EMI can be reduced to a very low level. The PCB layer stackup design examples given in this article will assume a layer spacing of 3 to 6 mils.

Electromagnetic shielding

From the perspective of signal routing, a good layering strategy should be to place all signal routing on one or several layers, which are close to the power layer or ground layer. For power supply, a good layering strategy should be that the power layer is adjacent to the ground layer, and the distance between the power layer and the ground layer is as small as possible. This is what we call the “layering” strategy.

PCB stacking

What kind of stacking strategy helps shield and suppress EMI? The following layered stacking scheme assumes that the power current flows on a single layer and single voltage or multiple voltages are distributed in different parts of the same layer. The case of multiple power planes is discussed later.

4-layer board

There are several potential problems with 4-layer board design. First, for a traditional four-layer board with a thickness of 62 mil, even if the signal layer is on the outer layer and the power and ground layers are on the inner layer, the distance between the power layer and the ground layer is still too large.

If cost requirement is the first priority, you can consider the following two alternatives to traditional 4-layer boards.

Both solutions can improve EMI suppression performance, but they are only applicable when the component density on the board is low enough and there is enough area around the components (to place the required power copper layer).

The first is the preferred option. The outer layers of the PCB are all ground layers, and the two middle layers are signal/power layers. The power supply on the signal layer is routed with wide lines, which can make the path impedance of the power supply current low and the impedance of the signal microstrip path also low. From the perspective of EMI control, this is the best 4-layer PCB structure available. The second solution uses the outer layer for power and ground, and the middle two layers for signals. This solution offers less improvement than the traditional 4-layer board, and the inter-layer impedance is as poor as the traditional 4-layer board.

If you want to control the trace impedance, the above stacking scheme must be very careful to arrange the traces under the power and ground copper islands. In addition, the copper islands on the power supply or ground layer should be interconnected as much as possible to ensure DC and low-frequency connectivity.

6-layer board

If the component density on a 4-layer board is relatively high, it is best to use a 6-layer board. However, some stacking schemes in the 6-layer board design do not provide good enough shielding effect on the electromagnetic field and have little effect on reducing the transient signal of the power bus. Two examples are discussed below.
In the first example, the power supply and ground are placed on the 2nd and 5th layers respectively. Since the power supply copper impedance is high, it is very unfavorable for controlling common mode EMI radiation. However, from the perspective of signal impedance control, this method is very correct.