Master the characteristics of IC packaging to achieve optimal EMI suppression performance
Placing decoupling capacitors directly inside the IC package can effectively control EMI and improve signal integrity. This article starts with the internal packaging of the IC, analyzes the source of EMI, the role of IC packaging in EMI control, and then proposes 11 design rules for effective EMI control, including package selection, pin structure considerations, output drivers, and decoupling capacitor design methods, etc., which will help design engineers choose the most suitable integrated circuit chip in the new design to achieve the best EMI suppression performance.
Existing system-level EMI control technologies include:
The circuit is enclosed in a Faraday box (note that the mechanical package containing the circuit should be sealed) to achieve EMI shielding;
Filtering and attenuation technology is used on the I/O port of the circuit board or system to achieve EMI control;
Strictly shield the electric and magnetic fields of the circuit board, or use appropriate design technology on the circuit board to strictly control the capacitance and inductance of the PCB routing and circuit board layer (self-shielding), thereby improving EMI performance.
EMI control usually requires the combination of the above technologies. Generally speaking, the closer to the EMI source, the lower the cost required to achieve EMI control. Integrated circuit chips on PCBs are the main energy source of EMI, so if you can deeply understand the internal characteristics of integrated circuit chips, you can simplify EMI control in PCB and system-level design.
PCB board-level and system-level design engineers usually think that the source of EMI they can access is PCB. Obviously, at the PCB design level, a lot of work can be done to improve EMI. However, when considering EMI control, design engineers should first consider the selection of IC chips. Certain characteristics of integrated circuits such as package type, bias voltage and chip process technology (such as CMOS, ECL, TTL) have a great impact on electromagnetic interference. This article will focus on these issues and explore the impact of IC on EMI control.
1.Source of EMI
During the conversion of digital integrated circuits from logic high to logic low or from logic low to logic high, the square wave signal frequency generated at the output end is not the only frequency component that causes EMI. The square wave contains sinusoidal harmonic components with a wide frequency range, which constitute the EMI frequency components that engineers are concerned about. The highest EMI frequency is also called the EMI emission bandwidth, which is a function of the signal rise time rather than the signal frequency. The formula for calculating EMI emission bandwidth is:
F=0.35/Tr
Where: F is the frequency in GHz; Tr is the signal rise time or fall time in ns (nanoseconds).
It is not difficult to see from the above formula that if the switching frequency of the circuit is 50MHz, and the rise time of the integrated circuit chip used is 1ns, then the highest EMI emission frequency of the circuit will reach 350MHz, which is much greater than the switching frequency of the circuit. If the rise time of the IC is 500ps, then the highest EMI emission frequency of the circuit will be as high as 700MHz. As we all know, every voltage value in the circuit corresponds to a certain current, and every current has a corresponding voltage. When the output of the IC changes from logic high to logic low or from logic low to logic high, these signal voltages and signal currents will generate electric and magnetic fields, and the highest frequency of these electric and magnetic fields is the emission bandwidth. The strength of the electric and magnetic fields and the percentage of external radiation are not only a function of the signal rise time, but also depend on the control of the capacitance and inductance of the signal path from the signal source to the load point. Here, the signal source is located inside the IC of the PCB board, and the load is located inside other ICs, which may or may not be on the PCB. In order to effectively control EMI, it is necessary to pay attention not only to the capacitance and inductance of the IC chip itself, but also to the capacitance and inductance on the PCB.
When the coupling between the signal voltage and the signal loop is not tight, the capacitance of the circuit will decrease, and the suppression of the electric field will be weakened, thereby increasing EMI; the same situation exists in the current in the circuit. If the current is not well coupled with the return path, the inductance of the loop will inevitably increase, thereby enhancing the magnetic field, and ultimately leading to increased EMI. In other words, poor control of the electric field usually leads to poor magnetic field suppression. The measures used to control the electromagnetic field in the circuit board are roughly similar to those used to suppress the electromagnetic field in the IC package. Just as in the case of PCB design, IC package design will greatly affect EMI.
A considerable part of the electromagnetic radiation in the circuit is caused by voltage transients in the power bus. When the output stage of the IC jumps and drives the connected PCB line to logic “high”, the IC chip will absorb current from the power supply to provide the energy required by the output stage. For the ultra-high frequency current generated by the continuous conversion of the IC, the power bus starts from the decoupling network on the PCB and ends at the output stage of the IC. If the signal rise time of the output stage is 1.0ns, then the IC must absorb enough current from the power supply in such a short time of 1.0ns to drive the transmission line on the PCB. The transient change of the voltage on the power bus depends on the inductance on the power bus path, the absorbed current, and the transmission time of the current. The transient change of voltage is defined by the following formula:
V=Ldi/dt, where: L is the value of the inductance on the current transmission path; di represents the change of current in the time interval of signal rise; dt represents the transmission time of current (signal rise time).
Since the IC pins and internal circuits are part of the power bus, and the absorption current and the rise time of the output signal also depend on the process technology of the IC to a certain extent, choosing a suitable IC can largely control all three factors mentioned in the above formula.
2.The role of IC packaging in electromagnetic interference control
IC packaging usually includes: silicon-based chips, a small internal PCB and pads. The silicon-based chip is mounted on a small PCB, and the connection between the silicon-based chip and the pad is achieved through binding wires. In some packages, direct connection can also be achieved. The small PCB realizes the connection between the signal and power on the silicon-based chip and the corresponding pins on the IC package, thus realizing the external extension of the signal and power nodes on the silicon-based chip. The transmission path of the power and signal throughout the IC includes: the silicon-based chip, the connection between the small PCB, the PCB routing, and the input and output pins of the IC package. The control of capacitance and inductance (corresponding to the electric field and magnetic field) depends largely on the design of the entire transmission path. Certain design features will directly affect the capacitance and inductance of the entire IC chip package.
First, look at the connection method between the silicon-based chip and the internal small circuit board.
Many IC chips use binding wires to achieve the connection between the silicon-based chip and the internal small circuit board. This is an extremely thin flying wire between the silicon-based chip and the internal small circuit board. This technology is widely used because the coefficient of thermal expansion (CTE) of the silicon chip and the internal small circuit board is similar. The chip itself is a silicon-based device, and its CTE is very different from the CTE of typical PCB materials (such as epoxy resin). If the electrical connection points of the silicon chip are directly mounted on the internal small PCB, then after a relatively short period of time, the change in temperature inside the IC package causes thermal expansion and contraction, and this type of connection will fail due to fracture. Wirebonds are a lead method that adapts to this special environment. They can withstand a lot of bending deformation without breaking easily.
The problem with wirebonds is that the increase in the current loop area of each signal or power line will lead to an increase in inductance value.
A good design to achieve a lower inductance value is to achieve a direct connection between the silicon chip and the internal PCB, that is, the connection points of the silicon chip are directly bonded to the pads of the PCB. This requires the selection of a special PCB substrate material, which should have a very low CTE. The selection of this material will lead to an increase in the overall cost of the IC chip, so the chip using this process technology is not common, but as long as this IC that directly connects the silicon-based chip to the carrier PCB exists and is feasible in the design plan, then using such an IC device is a better choice.
Generally speaking, in IC package design, reducing inductance and increasing capacitance between the signal and the corresponding loop or between the power supply and the ground is the first consideration in the selection of integrated circuit chips. For example, compared with large-pitch surface mounting, small-pitch surface mounting should be preferred to IC chips packaged with small-pitch surface mounting technology, and both types of surface mounting technology packaged IC chips are better than through-hole lead type packaging. BGA packaged IC chips have the lowest lead inductance compared to any commonly used package type. From the perspective of capacitance and inductance control, small packages and finer pitches usually always represent improved performance.
An important feature of lead structure design is the allocation of pins.
Since the size of the inductance and capacitance values depends on the proximity between the signal or power supply and the return path, sufficient return paths should be considered.
Power and ground pins should be allocated in pairs, each power pin should have a corresponding ground pin adjacent to it, and multiple power and ground pin pairs should be allocated in this lead structure. Both of these features will greatly reduce the loop inductance between power and ground, help reduce voltage transients on the power bus, and thus reduce EMI. Due to customary reasons, many IC chips on the market now do not fully follow the above design rules, but IC designers and manufacturers deeply understand the advantages of this design method, so IC manufacturers pay more attention to the connection of power when designing and releasing new IC chips.
Ideally, an adjacent signal return pin (such as a ground pin) should be allocated to each signal pin. In reality, this is not the case.
Even the most avant-garde IC manufacturers do not allocate the pins of IC chips in this way, but use other compromise methods. In BGA packaging, an effective design method is to set a signal return pin in the center of each group of eight signal pins. Under this pin arrangement, each signal is only one pin away from the signal return path. For ICs in quad flat package (QFP) or other gull wing packages, it is unrealistic to place a signal return path in the center of the signal group. Even so, a signal return pin must be placed every 4 to 6 pins. It should be noted that different IC process technologies may use different signal return voltages. Some ICs use ground pins (such as TTL devices) as signal return paths, while some ICs use power pins (such as most ECL devices) as signal return paths, and some ICs use both power and ground pins (such as most CMOS devices) as signal return paths. Therefore, design engineers must be familiar with the IC chip logic series used in the design and understand their related working conditions.
The reasonable distribution of power and ground pins in IC chips can not only reduce EMI, but also greatly improve the ground bounce effect. When the device driving the transmission line tries to pull the transmission line to logic low, the ground bounce reflection still maintains the transmission line above the logic low threshold level, and the ground bounce reflection may cause circuit failure or malfunction.
Another important issue that needs to be paid attention to in IC packaging is the PCB design inside the chip.
The internal PCB is usually the largest component of the IC package. If the capacitance and inductance can be strictly controlled during the internal PCB design, the overall EMI performance of the design system will be greatly improved. If this is a two-layer PCB board, at least one side of the PCB board is required to be a continuous ground plane layer, and the other layer of the PCB board is the wiring layer for power and signals. The more ideal situation is a four-layer PCB board, with the two middle layers being the power and ground plane layers, and the two outer layers being the wiring layers for signals. Since the PCB inside the IC package is usually very thin, the design of the four-layer board structure will lead to two high-capacitance, low-inductance wiring layers, which are particularly suitable for power distribution and input and output signals that need to be strictly controlled in and out of the package. The low-impedance plane layer can greatly reduce the voltage transients on the power bus, thereby greatly improving the EMI performance. This controlled signal line is not only conducive to reducing EMI, but also plays an important role in ensuring the integrity of the signals in and out of the IC.
3.Other related IC process technology issues
The power supply voltage Vcc of the integrated circuit chip bias and drive is an important issue to pay attention to when selecting an IC. The current absorbed from the IC power pin mainly depends on the voltage value and the impedance of the transmission line (PCB line and ground return path) driven by the output stage of the IC chip. When the IC chip with a 5V power supply voltage drives a 50Ω transmission line, the absorbed current is 100mA; when the IC chip with a 3.3V power supply voltage drives the same 50Ω transmission line, the absorbed current will be reduced to 66mA; when the IC chip with a 1.8V power supply voltage drives the same 50Ω transmission line, the absorbed current will be reduced to 36mA. It can be seen that in the formula V=Ldi/dt, the reduction of the driving current from 100mA to 36mA can effectively reduce the voltage transient V, thereby reducing EMI. The signal voltage swing of the low voltage differential signal device (LVDS) is only a few hundred millivolts. It can be imagined that such device technology will significantly improve EMI.
The decoupling of the power supply system is also an issue that deserves special attention.
The current absorbed by the IC output stage through the IC power pin is provided by the decoupling network on the circuit board. One possible way to reduce the voltage drop on the power bus is to shorten the distribution path between the decoupling capacitor and the IC output stage. This will reduce the “L” term in the “Ldi/dt” expression. As the rise time of IC devices is getting faster and faster, the only way to implement it when designing PCB boards is to shorten the distribution path between the decoupling capacitor and the IC output stage as much as possible. One of the most direct solutions is to place all power decoupling inside the IC. The ideal situation is to place it directly on the silicon chip and close to the driven output stage. For IC manufacturers, this is not only expensive but also difficult to achieve. However, if the decoupling capacitor is placed directly on the PCB board inside the IC package and directly connected to the pins of the silicon chip, the design cost will increase the least and contribute the most to EMI control and improve signal integrity. Currently, only a few high-end microprocessors use this technology, but IC manufacturers are increasingly interested in this technology. It can be foreseen that such design technology will be widely used in large-scale, high-power IC designs in the future.
The capacitors designed inside the IC package are usually very small (less than a few hundred pico-farads), so system design engineers still need to install decoupling capacitors with values between 0.001uF and 0.1uF on the PCB. However, the small capacitors inside the IC package can suppress the high-frequency components in the output waveform
