Basic knowledge of component packaging
Packaging refers to connecting the circuit pins on the silicon chip to the external connector with wires so as to connect with other devices. The packaging form refers to the shell used to install the semiconductor integrated circuit chip. It not only plays the role of installing, fixing, sealing, protecting the chip and enhancing the electrical and thermal performance, but also connects the contacts on the chip to the pins of the package shell with wires, and these pins are connected to other devices through the wires on the printed circuit board, thereby realizing the connection between the internal chip and the external circuit. Because the chip must be isolated from the outside world to prevent impurities in the air from corroding the chip circuit and causing a decrease in electrical performance. On the other hand, the packaged chip is also easier to install and transport. Since the quality of packaging technology also directly affects the performance of the chip itself and the design and manufacture of the PCB (printed circuit board) connected to it, it is crucial. An important indicator to measure the advancement of a chip packaging technology is the ratio of chip area to packaging area. The closer this ratio is to 1, the better.
The main factors to consider when packaging:
- The ratio of chip area to package area should be as close to 1:1 as possible to improve packaging efficiency;
- The pins should be as short as possible to reduce delays, and the distance between pins should be as far as possible to ensure no interference and improve performance;
- Based on the requirements of heat dissipation, the thinner the package, the better. Packages are mainly divided into two types: DIP dual in-line package and SMD patch package. From the structural aspect, the package has experienced the earliest transistor TO (such as TO-89, TO92) package development to dual in-line package, and then PHILIP developed SOP small outline package, and then gradually derived SOJ (J-type pin small outline package), TSOP (thin small outline package), VSOP (very small outline package), SSOP (shrink SOP), TSSOP (thin shrink SOP) and SOT (small outline transistor), SOIC (small outline integrated circuit), etc.
From the material medium, including metal, ceramic, plastic, plastic, many circuits with high-intensity working conditions such as military and aerospace levels still have a large number of metal packages. The package has roughly gone through the following development process: Structure: TO->DIP->PLCC->QFP->BGA->CSP; Material: metal, ceramic->ceramic, plastic->plastic; Pin shape: long lead straight insertion->short lead or leadless mounting->ball bump; Assembly method: through-hole insertion->surface assembly->direct installation Specific package form
1.SOP/SOIC package
SOP is the abbreviation of Small Outline Package in English, that is, small outline package. SOP packaging technology was successfully developed by Philips in 1968-1969, and later gradually derived SOJ (J-type pin small outline package), TSOP (thin small outline package), VSOP (very small outline package), SSOP (shrink SOP), TSSOP (thin shrink SOP) and SOT (small outline transistor), SOIC (small outline integrated circuit), etc.
2.DIP package
DIP is the abbreviation of Double In-line Package in English, that is, dual in-line package. One of the plug-in packages, the pins are led out from both sides of the package, and the packaging materials are plastic and ceramic. DIP is the most popular plug-in package, and its application range includes standard logic IC, memory LSI, microcomputer circuit, etc.
3.PLCC package
PLCC is the abbreviation of Plastic Leaded Chip Carrier in English, that is, plastic J lead chip package. PLCC package method, the shape is square, 32-pin package, there are pins on all sides, and the size is much smaller than DIP package. PLCC package is suitable for installation and wiring on PCB using SMT surface mounting technology, and has the advantages of small size and high reliability.
4.TQFP package
TQFP is the abbreviation of thin quad flat package in English, that is, thin plastic quad flat package. The quad flat package (TQFP) process can effectively utilize space, thereby reducing the requirements for the size of the printed circuit board space. Due to the reduction in height and volume, this packaging process is very suitable for applications with high space requirements, such as PCMCIA cards and network devices. Almost all ALTERA’s CPLD/FPGA have TQFP packages.
5.PQFP package
PQFP is the abbreviation of Plastic Quad Flat Package in English, that is, plastic quad flat package. The distance between the chip pins of PQFP package is very small, and the pins are very thin. Generally, large-scale or ultra-large-scale integrated circuits use this package form, and the number of pins is generally more than 100.
6.TSOP package
TSOP is the abbreviation of Thin Small Outline Package in English, that is, thin small size package. A typical feature of TSOP memory packaging technology is that pins are made around the packaged chip. TSOP is suitable for installation and wiring on PCB (printed circuit board) using SMT technology (surface mounting technology). When the TSOP package size is reduced, the parasitic parameters (when the current changes greatly, the output voltage disturbance is caused) are reduced, which is suitable for high-frequency applications, easy to operate, and has high reliability.
7.BGA package
BGA is the abbreviation of Ball Grid Array Package in English, that is, ball grid array package.
In the 1990s, with the advancement of technology, the integration of chips continued to increase, the number of I/O pins increased sharply, the power consumption also increased, and the requirements for integrated circuit packaging became more stringent. In order to meet the needs of development, BGA packaging began to be used in production.
Memory packaged with BGA technology can increase the memory capacity by two to three times without changing the volume. Compared with TSOP, BGA has a smaller volume, better heat dissipation and electrical performance. BGA packaging technology has greatly increased the storage capacity per square inch. The volume of memory products using BGA packaging technology is only one-third of that of TSOP packaging at the same capacity. In addition, compared with the traditional TSOP packaging method, BGA packaging has a faster and more effective heat dissipation path.
The I/O terminals of BGA packaging are distributed under the package in the form of circular or columnar solder joints in an array. The advantage of BGA technology is that although the number of I/O pins has increased, the pin spacing has not decreased but increased, thereby improving the assembly yield rate; although its power consumption has increased, BGA can be welded using the controlled collapse chip method, which can improve its electrothermal performance; the thickness and weight are reduced compared with previous packaging technologies; parasitic parameters are reduced, signal transmission delay is small, and the frequency of use is greatly increased; coplanar welding can be used for assembly, and the reliability is high.
When it comes to BGA packaging, Kingmax’s patented TinyBGA technology cannot be ignored. TinyBGA’s full name in English is Tiny Ball GridArray (small ball grid array package), which is a branch of BGA packaging technology. It was successfully developed by Kingmax in August 1998. The ratio of its chip area to package area is not less than 1:1.14, which can increase the memory capacity by 2 to 3 times without changing the volume. Compared with TSOP packaged products, it has a smaller volume, better heat dissipation and electrical performance.
The volume of memory products using TinyBGA packaging technology is only 1/3 of that of TSOP packaging under the same capacity. The pins of TSOP packaged memory are led out from the four sides of the chip, while TinyBGA is led out from the center of the chip. This method effectively shortens the signal transmission distance, and the length of the signal transmission line is only 1/4 of the traditional TSOP technology, so the signal attenuation is also reduced. This not only greatly improves the chip’s anti-interference and anti-noise performance, but also improves the electrical performance.
The chip packaged with TinyBGA can withstand up to 300MHz external frequency, while the traditional TSOP packaging technology can only withstand up to 150MHz external frequency.
The memory packaged in TinyBGA is also thinner (package height is less than 0.8mm), and the effective heat dissipation path from the metal substrate to the heat sink is only 0.36mm. Therefore, TinyBGA memory has higher thermal conductivity efficiency, is very suitable for long-term running systems, and has excellent stability. (Power Network)
