A new approach to solving signal problems in high-speed PCB design

In high-speed PCB design, signal integrity issues are increasingly affecting the reliability of circuit design. To solve signal integrity problems, design engineers are investing more time and energy in the constraint definition stage of board design. By using design-oriented signal analysis tools early in the design, running multiple simulations, and carefully planning the board topology, comprehensive design constraints for electrical and physical characteristics can be formulated to avoid EMI and other related problems.

The current typical design environment is mostly oriented to the later stage of design, with board drawing as the main consideration. Design tool providers are now starting to address these new design challenges. But design engineers need a new approach to solve the increasingly prominent high-speed design problems in design, using this approach, design engineers can solve problems early in the design.

Tighter tool integration

The key to finding and solving these high-speed signal problems without relying on expensive and time-consuming board testing steps is to perform extensive signal analysis before the board is designed. When design engineers find these problems, they can ensure the first-time success of the circuit design by changing the routing and circuit layer distribution, defining the routing topology of the clock line, and selecting components with specific speeds.
However, previous signal integrity analysis tools have great limitations, either not easy to use or not capable of analyzing the entire design. Therefore, design engineers can only rely on experience to determine the key circuit networks that need to be focused on, or rely on signal integrity comprehensive analysis tools for analysis.

Recently, design tools have begun to make new breakthroughs and develop effective analysis tools for high-speed design problems.

Taking the signal integrity analysis tools provided by Innovationa as an example, the company’s HyperLynx tool group is easy to use and can provide powerful signal integrity analysis functions before and after the circuit board is drawn. One of its outstanding features is that the user interface is very friendly, which allows design engineers to quickly analyze the “possible situations” they have imagined and experiment with issues such as terminal topology, so as to quickly find the best solution that meets performance and reliability. For engineers who deal with highly complex circuit boards and systems, Innovationa’s XTK signal integrity verification tool group and ePlanner signal integrity planning environment provide advanced algorithms for ultra-high-speed signal integrity analysis and some mature verification functions, including topology analysis, high-speed scanning and loss lines, Monte Carlo method, and advanced algorithms for signal integrity analysis.

In the past, design engineers had to choose between Hyperlynx and XTK.

Recently, Innoveda has realized the connection between these two key signal integrity analysis tools, which integrates the two tools together and can be used simultaneously in one design, which can effectively shorten the design cycle. Usually, HyperLynx is initially used as a tool for high-speed PCB signal analysis, while XTK and ePlanner are used for more complex topology analysis and constraint generation.

Enhanced wiring capabilities

After determining the wiring rules, design engineers begin to turn to the physical implementation of the design. Conventional PCB drawing tools provide comprehensive component selection capabilities, can set board layers, assign constraint rules and manage the placement of all components on the board. Good tools must be easy to use, can automatically manage all design constraints, and produce the final circuit board design.

But this is not enough in a high-speed design environment.

PCB drawing tools must provide more comprehensive solutions. At present, some designs are usually very complex and have short development time. Design engineers can no longer use the manual drawing method of the past, otherwise it is time-consuming and error-prone. In order to maximize work efficiency and solve a large number of signal analysis problems, design engineers need a tool that allows them to complete wiring in batch mode and interactively.

Innoveda’s latest release of PowerPCB 5.0 meets this design requirement.

The shape- and rule-based board design system includes a high-speed design option, BlazeRouter HSD (High Speed ​​Design), which allows automatic routing based on high-speed constraints, including min/max lengths, matched lengths, and differential pairs (differential pairs). Such constraints can be set anywhere in the rule system, and BlazeRouter HSD automatically implements the design according to these rules. This allows designers to set and protect critical circuit topologies to ensure that critical signals are connected in the correct order.

The tool also adds an interactive routing editor for designers who prefer manual routing, and provides a lot of special support for constraint-generated nets.

The new Fast Interactive Routing Editor (FIRE) has multiple design rule checking (DRC) modes and new routing editing capabilities. Designers can automatically add “Z” jacks, find differential pairs, monitor trace lengths, or design according to specific constraint rules. This makes it easier for designers to achieve dense routing designs and achieve greater routing density on the fewest board layers.

In addition, the tool provides a graphical feedback feature to indicate to designers the impact of a routing choice on other nets on the board. In the past, it was difficult for designers to know how changes to critical nets would affect other parts of the design. BlazeRouter HSD presents these previously difficult-to-understand effects in a graphical form, using different colors and brightness to represent different effects. This helps designers understand the possible impact of each routing choice.

Building a complete design methodology

The above tools represent the most significant development in solving the high-speed problems that are prevalent in today’s circuit board design. However, design tools must also add more functions to adapt to the rapidly increasing clock speeds and complexity of circuit board design, especially the need to replace the current multi-point design tools with an integrated design methodology.

What design flow does the new methodology have?

In order to solve the high-speed problems in the critical path, new functions must be added at the initial design definition stage of the process. To achieve this goal, the new methodology must have powerful simulation and analysis capabilities. At the same time, it must be able to understand the key data of the circuit board design, especially information about component availability and cost. Ideally, the design platform can achieve collaboration within the entire company through the design engineer, and the design engineer can communicate design ideas not only among the design engineers through the network, but also with other departments such as procurement and production.

At the same time, the design of high-speed circuit boards relies heavily on a constraint generation method.

Currently, design engineers input electronic design data and design constraints into board drawing software to implement circuit design, but signal integrity issues and the increasing complexity of board design have further complicated the problem. To solve signal integrity issues on these high-speed and complex boards, they must simulate and synthesize the design before drawing the board. This puts new demands on the design environment, and design engineers must set constraints from electrical characteristics to manufacturing processes. In an ideal design platform, design engineers can not only set electrical characteristics rules for parameters such as trace length, electromagnetic interference or crosstalk, but also set component placement rules for component spacing, height restrictions and rotation angles.

To quickly generate such constraints, the design environment must have powerful topology analysis and “what if” analysis capabilities.

It is best to allow design engineers to design and simulate network topologies in circuit diagram form, allow the use of signal integrity analysis engines to change topology parameters in multiple simulations, and then explore various termination schemes and make them work with delay constraints, circuit layer options and trace spacing to minimize the impact on signal integrity. This capability should also be tightly integrated with component placement and linked to planning capabilities so that designers can define initial component placement and understand the performance of routing strategies. In short, the new design environment must provide powerful constraint management capabilities so that designers can organize and manage a large amount of information.

Not only that, this new approach to high-speed design must also provide verification capabilities in the later stages of the development process. In the past, circuit designers only performed post-routing verification when critical networks existed on the board, and a complete comprehensive verification of the entire circuit board design was considered complex and time-consuming. But this view is changing because the complex interactions between thousands of networks in today’s high-speed circuit board designs are difficult to predict. The only way to ensure the reliability of the design is to perform a thorough overall simulation of the entire routing design.