Full introduction to PCB vias

Via is one of the important components of multi-layer PCBs, and the cost of drilling holes usually accounts for 30% to 40% of the cost of PCB board manufacturing. Simply put, every hole on a PCB can be called a via. From the perspective of function, vias can be divided into

two categories:
One is used as an electrical connection between layers;
The other is used to fix or position devices.

If from the perspective of process technology, these vias are generally divided into three categories, namely blind vias, buried vias, and through vias. Blind vias are located on the top and bottom surfaces of a printed circuit board and have a certain depth.

They are used to connect the surface circuits and the inner circuits below.

The depth of the holes usually does not exceed a certain ratio (aperture). Buried vias refer to connection holes located in the inner layers of a printed circuit board, which do not extend to the surface of the circuit board. The above two types of holes are located in the inner layers of the circuit board and are completed using the through-hole forming process before lamination.

During the via formation process, several inner layers may be overlapped.

The third type is called a through hole, which passes through the entire circuit board and can be used to achieve internal interconnection or as a component installation positioning hole. Since through-holes are easier to implement and have lower costs, most printed circuit boards use them instead of the other two types of vias. The vias mentioned below are considered as through-holes unless otherwise specified.

From a design perspective, a via is mainly composed of two parts:

the drill hole in the middle and the pad area around the drill hole, as shown in the figure below. The size of these two parts determines the size of the via. Obviously, in high-speed, high-density PCB design, designers always hope that the vias are as small as possible, so that more wiring space can be left on the board. In addition, the smaller the via, the smaller its own parasitic capacitance is, and it is more suitable for high-speed circuits.

However, the reduction in hole size also brings about an increase in cost, and the size of the via cannot be reduced indefinitely.

It is limited by process technologies such as drilling and plating: the smaller the hole, the longer it takes to drill, and the easier it is to deviate from the center position; and when the depth of the hole exceeds 6 times the diameter of the drill hole, it cannot be guaranteed that the hole wall can be evenly plated with copper. For example, the thickness (through hole depth) of a normal 6-layer PCB board is about 50 mil, so the minimum drilling diameter that PCB manufacturers can provide can only reach 8 mil.

2.Parasitic capacitance of vias

The via itself has parasitic capacitance to the ground. If the diameter of the isolation hole of the via on the ground layer is known to be D2, the diameter of the via pad is D1, the thickness of the PCB board is T, and the dielectric constant of the board substrate is ε, then the parasitic capacitance of the via is approximately: C=1.41εTD1/(D2-D1)

The parasitic capacitance of the via will have the main impact on the circuit by extending the rise time of the signal and reducing the speed of the circuit. For example, for a PCB board with a thickness of 50 mil, if a via with an inner diameter of 10 mil and a pad diameter of 20 mil is used, and the distance between the pad and the ground copper area is 32 mil, then we can use the above formula to approximate the parasitic

capacitance of the via: C = 1.41×4.4×0.050×0.020/(0.032-0.020) = 0.517pF, and the rise time change caused by this part of the capacitance is: T10-90 = 2.2C (Z0/2) = 2.2×0.517x (55/2) = 31.28ps. From these values, it can be seen that although the effect of the rise delay caused by the parasitic capacitance of a single via is not very obvious, if the via is used multiple times in the routing to switch between layers, the designer should still consider it carefully. 3. Parasitic inductance of vias

Similarly, parasitic capacitance and parasitic inductance exist in vias.

In the design of high-speed digital circuits, the harm caused by parasitic inductance of vias is often greater than the influence of parasitic capacitance. Its parasitic series inductance will weaken the contribution of bypass capacitance and reduce the filtering effect of the entire power supply system. We can use the following formula to simply calculate the parasitic inductance of a via: L=5.08h[ln(4h/d)+1] where L refers to the inductance of the via, h is the length of the via, and d is the diameter of the center drill hole. It can be seen from the formula that the diameter of the via has a small effect on the inductance, while the length of the via has the greatest impact on the inductance. Still using the above example, the inductance of the via can be calculated as: L=5.08×0.050[ln(4×0.050/0.010)+1]=1.015nH. If the rise time of the signal is 1ns, then its equivalent impedance is: XL=πL/T10-90=3.19Ω. Such impedance can no longer be ignored when there is a high-frequency current passing through. In particular, it should be noted that the bypass capacitor needs to pass through two vias when connecting the power layer and the ground layer, so the parasitic inductance of the via will increase exponentially.

2.Via design in high-speed PCB

Through the above analysis of the parasitic characteristics of vias, we can see that in high-speed PCB design, seemingly simple vias often bring great negative effects to the design of the circuit. In order to reduce the adverse effects of the parasitic effects of vias, the following can be done as much as possible in the design:

3.Considering both cost and signal quality, choose a reasonable size of via.

For example, for the 6-10 layer memory module PCB design, it is better to use 10/20Mil (drilling/pad) vias. For some high-density small-sized boards, you can also try to use 8/18Mil vias. Under current technical conditions, it is difficult to use smaller vias. For vias of power or ground, you can consider using a larger size to reduce impedance.

4.The two formulas discussed above show that using a thinner PCB board is conducive to reducing the two parasitic parameters of vias.

5.Try not to change layers for signal routing on the PCB board, that is, try not to use unnecessary vias.

6.The pins of power and ground should be drilled nearby, and the leads between the vias and the pins should be as short as possible, because they will
cause an increase in inductance. At the same time, the leads of power and ground should be as thick as possible to reduce impedance.

7.Place some grounded vias near the vias where the signal changes layers to provide the closest loop for the signal. You can even place a large number of redundant ground vias on the PCB board. Of course, you also need to be flexible and changeable when designing. The via model discussed above is the case where each layer has a pad. Sometimes, we can reduce or even remove the pads of some layers. Especially when the via density is very high, it may cause a broken groove to be formed in the copper layer, which will cut off the circuit. To solve this problem, in addition to moving the position of the via, we can also consider reducing the pad size of the via in the copper layer.