How to ensure signal integrity in PCB design

Signal integrity refers to the quality of the signal on the signal line, that is, the ability of the signal to respond with the correct timing and voltage in the circuit. If the signal in the circuit can reach the receiver with the required timing, duration and voltage amplitude, it can be determined that the circuit has good signal integrity. Conversely, when the signal cannot respond normally, a signal integrity problem occurs.

With the increasing use of high-speed devices and the design of high-speed digital systems, system data rates, clock rates and circuit density are constantly increasing. In this design, the system has fast slope transients and high operating frequencies, and cables, interconnects, printed circuit boards (PCBs) and silicon chips will exhibit behaviors that are completely different from low-speed designs, that is, signal integrity problems will occur.

Signal integrity problems can cause or directly bring about signal distortion, timing errors, incorrect data, addresses, control lines and system errors, and even cause system crashes, which has become a very noteworthy issue in high-speed product design. This article first introduces the problem of PCB signal integrity, then explains the steps of PCB signal integrity, and finally introduces how to ensure the signal integrity of PCB design.

PCB signal integrity issues include:

PCB signal integrity issues mainly include signal reflection, crosstalk, signal delay and timing errors.

1. Reflection: When the signal is transmitted on the transmission line, when the characteristic impedance of the transmission line on the high-speed PCB does not match the source impedance or load impedance of the signal, the signal will be reflected, causing overshoot, undershoot and ringing in the signal waveform. Overshoot refers to the first peak (or valley) of the signal jump, which is an additional voltage effect above the power supply level or below the reference ground level; undershoot refers to the next valley (or peak) of the signal jump. Excessive overshoot voltage often causes damage to the device for a long time, undershoot reduces the noise tolerance, and ringing increases the time required for the signal to stabilize, thereby affecting the system timing.
2. Crosstalk: In PCB, crosstalk refers to the unwanted noise interference caused by electromagnetic energy to the adjacent transmission line through mutual capacitance and mutual inductance coupling when the signal propagates on the transmission line. It is caused by the interaction of electromagnetic fields caused by different structures in the same area. Mutual capacitance induces coupling current, which is called capacitive crosstalk; while mutual inductance induces coupling voltage, which is called inductive crosstalk. On PCB, crosstalk is related to the length of the trace, the spacing between signal lines, and the condition of the reference ground plane.
3. Signal delay and timing error: The signal is transmitted at a limited speed on the conductor of the PCB. There is a transmission delay between the signal from the driver end to the receiver end. Excessive signal delay or mismatched signal delay may lead to timing errors and confusion of logic device functions.

High-speed digital system design analysis based on signal integrity analysis can not only effectively improve product performance, but also shorten product development cycle and reduce development costs. In the case of digital systems developing towards high speed and high density, it is urgent and necessary to master this design tool. With the continuous improvement and improvement of signal integrity analysis models and calculation and analysis algorithms, the digital system design method using signal integrity for computer design and analysis will be widely and comprehensively applied.

Steps for PCB signal integrity:

1.Preparation before design

Before the design begins, you must think about and determine the design strategy in advance, so as to guide tasks such as component selection, process selection and circuit board production cost control. As far as SI is concerned, it is necessary to conduct research in advance to form a plan or design criteria to ensure that the design results do not have obvious SI problems, crosstalk or timing problems.

2.Circuit board stacking

Some project groups have great autonomy in determining the number of PCB layers, while others do not have this autonomy, so it is important to understand where you are.

Other important questions include: What is the expected manufacturing tolerance?

What is the expected insulation constant on the circuit board? What is the allowable error of line width and spacing? What is the allowable error of the thickness and spacing of the ground layer and signal layer? All this information can be used in the pre-wiring stage.

Based on the above data, you can choose the stacking.

Note that almost every PCB that is inserted into other circuit boards or backplanes has thickness requirements, and most circuit board manufacturers have fixed thickness requirements for the different types of layers they can manufacture, which will greatly restrict the number of final stacking. You may be tempted to work closely with your manufacturer to define the number of layer stack-ups. Impedance control tools should be used to generate target impedance ranges for different layers, taking into account the manufacturing tolerances provided by the manufacturer and the effects of adjacent routing.

In an ideal situation where the signal is intact, all high-speed nodes should be routed on impedance-controlled inner layers (such as striplines). To optimize SI and keep the board decoupled, ground/power planes should be placed in pairs whenever possible. If you can only have one ground/power plane pair, you’ll have to make do. If there are no power planes at all, you may have SI issues by definition. You may also encounter a situation where it is difficult to simulate or simulate the performance of the board before the return path for the signal is defined.

3.Crosstalk and Impedance Control

Coupling from adjacent signal lines will cause crosstalk and change the impedance of the signal lines. Coupling analysis of adjacent parallel signal lines may determine the “safe” or expected spacing (or parallel routing length) between signal lines or between types of signal lines. For example, if you want to limit the crosstalk from the clock to the data signal node to less than 100mV, but keep the signal traces parallel, you can find the minimum allowable spacing between signals on any given routing layer through calculation or simulation. At the same time, if the design contains impedance-critical nodes (either clocks or dedicated high-speed memory architectures), you must place the routing on one (or several) layers to get the desired impedance.

4.Important high-speed nodes

Delay and skew are key factors that must be considered for clock routing. Because of strict timing requirements, such nodes usually must use termination devices to achieve the best SI quality. These nodes should be determined in advance, and the time required to adjust component placement and routing should be planned to adjust the pointers of signal integrity design.

5.Technology selection

Different drive technologies are suitable for different tasks. Is the signal point-to-point or point-to-multiple taps? Is the signal output from the circuit board or stays on the same circuit board? What is the allowable skew and noise margin? As a general rule of signal integrity design, the slower the conversion speed, the better the signal integrity. There is no reason to use a 500PS rise time for a 50MHZ clock. A 2-3NS slew rate control device must be fast enough to ensure SI quality and help solve problems such as output synchronous switching (SSO) and electromagnetic compatibility (EMC).

The advantages of drive technology can be found in new FPGA programmable technology or user-defined ASICs. With these custom (or semi-custom) devices, you have a lot of room to select drive amplitude and speed. In the early stage of design, meet the requirements of FPGA (or ASIC) design time and determine the appropriate output selection, including pin selection if possible.

At this stage of design, obtain appropriate simulation models from IC suppliers. In order to effectively cover SI simulation, you will need an SI simulation program and corresponding simulation models (possibly IBIS models).

Finally, you should establish a series of design guidelines in the pre-wiring and routing stages, which include: target layer impedance, routing spacing, preferred device process, important node topology and termination planning.

6.Pre-wiring stage

The basic process of pre-wiring SI planning is to first define the input parameter range (drive amplitude, impedance, tracking speed) and possible topology range (minimum/maximum length, short line length, etc.), then run each possible simulation combination, analyze the timing and SI simulation results, and finally find an acceptable range of values.

Next, interpret the working range as routing constraints for PCB routing. Different software tools can be used to perform this type of “cleaning” preparation, and the routing program can automatically handle this type of routing constraints. For most users, timing information is actually more important than SI results, and the results of interconnect simulation can change the routing to adjust the timing of the signal path.

In other applications, this process can be used to determine the placement of pins or devices that are incompatible with the system timing pointer. At this time, it is possible to completely determine the nodes that need to be manually routed or the nodes that do not need termination. For programmable devices and ASICs, the output driver selection can also be adjusted at this time to improve SI design or avoid the use of discrete termination devices.

7.Post-routing SI simulation

In general, SI design guidelines are difficult to guarantee that there will be no SI or timing problems after the actual routing is completed. Even if the design is guided by the guidelines, unless you can continuously and automatically check the design, there is no guarantee that the design fully complies with the guidelines, so problems are inevitable. Post-routing SI simulation checks will allow planned breaking (or changes) of design rules, but this is only necessary work for cost considerations or strict routing requirements.

8.Post-manufacturing stage

Taking the above measures can ensure the SI design quality of the circuit board. After the circuit board assembly is completed, it is still necessary to place the circuit board on the test platform and use an oscilloscope or TDR (time domain reflectometer) to measure and compare the actual circuit board with the expected results of the simulation. These measurement data can help you improve the model and manufacturing parameters so that you can make better (less constrained) decisions in the next pre-design investigation.

9.Model selection

There are many articles on model selection. Engineers who perform static timing verification may have noticed that although all data can be obtained from the device data sheet, it is still difficult to build a model. The SI simulation model is just the opposite. The model is easy to build, but the model data is difficult to obtain. In essence, the only reliable source of SI model data is the IC supplier, who must maintain a tacit cooperation with the design engineer. The IBIS model standard provides a consistent data carrier, but the establishment of the IBIS model and its quality assurance are costly. IC suppliers still need to be driven by market demand for this investment, and circuit board manufacturers may be the only demand-side market.

PCB design method to ensure signal integrity:

By summarizing the factors that affect signal integrity, the following aspects can be considered to better ensure signal integrity during the PCB design process.

(1) Circuit design considerations. This includes controlling the number of synchronous switching outputs and the maximum edge rate (dI/dt and dV/dt) of each unit to obtain the lowest and acceptable edge rate; selecting differential signals for high-output functional blocks (such as clock drivers); terminating passive components (such as resistors, capacitors, etc.) on the transmission line to achieve impedance matching between the transmission line and the load.

(2) Minimize the length of parallel wiring.

(3) Place components away from I/O interconnect interfaces and other areas susceptible to interference and coupling, and minimize the spacing between components.

(4) Shorten the distance between signal traces and reference planes.

(5) Reduce trace impedance and signal drive level.

(6) Terminal matching. Terminal matching circuits or matching components can be added.

(7) Avoid parallel routing and provide sufficient spacing between routing lines to reduce inductive coupling.