How to solve the EMI problem in multi-layer PCB design?

Placing capacitors of appropriate capacity reasonably near the power pins of IC can make the jump of IC output voltage faster. However, the problem does not end there. Due to the limited frequency response characteristics of capacitors, capacitors cannot generate the harmonic power required to drive IC output cleanly over the full frequency band. In addition, the transient voltage formed on the power bus will form a voltage drop across the inductor of the decoupling path. These transient voltages are the main source of common-mode EMI interference.

How should we solve these problems?

As far as the IC on our circuit board is concerned, the power layer around the IC can be regarded as an excellent high-frequency capacitor, which can collect the energy leaked by the discrete capacitor that provides high-frequency energy for clean output. In addition, the inductance of an excellent power layer should be small, so that the transient signal synthesized by the inductor is also small, thereby reducing common-mode EMI.

Of course, the connection from the power layer to the IC power pin must be as short as possible, because the rising edge of the digital signal is getting faster and faster, it is best to connect directly to the pad where the IC power pin is located, which is another discussion.

In order to control common-mode EMI, the power layer should help decoupling and have a low enough inductance.

This power layer must be a pair of well-designed power layers. Some people may ask, how good is good? The answer to the question depends on the layering of the power supply, the material between the layers, and the operating frequency (i.e., the function of the IC rise time). Usually, the spacing of the power layer is 6mil, and the interlayer is FR4 material, then the equivalent capacitance of the power layer per square inch is about 75pF. Obviously, the smaller the layer spacing, the greater the capacitance.

There are not many devices with a rise time of 100 to 300ps, but according to the current development speed of IC, the devices with a rise time in the range of 100 to 300ps will occupy a high proportion. For circuits with a rise time of 100 to 300ps, 3mil layer spacing will no longer be applicable to most applications. At that time, it is necessary to adopt a layering technology with a layer spacing less than 1mil and replace the FR4 dielectric material with a material with a very high dielectric constant. Now, ceramics and ceramic plastics can meet the design requirements of circuits with a rise time of 100 to 300ps.

Although new materials and new methods may be adopted in the future, for today’s common 1 to 3ns rise time circuits, 3 to 6mil layer spacing and FR4 dielectric materials, it is usually sufficient to handle high-end harmonics and keep transient signals low enough, that is, common-mode EMI can be reduced very low. The PCB layer stacking design example given in this article will assume that the layer spacing is 3 to 6mil.

From the perspective of signal routing, a good layering strategy should be to put all signal routing on one or several layers, which are close to the power layer or ground layer. For power supply, a good layering strategy should be that the power layer is adjacent to the ground layer, and the distance between the power layer and the ground layer is as small as possible. This is what we call the “layering” strategy.

PCB stacking
4-layer board

There are several potential problems in the design of 4-layer board. First, for the traditional 62mil thick four-layer board, even if the signal layer is on the outer layer and the power and ground layers are on the inner layer, the spacing between the power layer and the ground layer is still too large.

If cost requirements are the first priority, the following two alternatives to traditional 4-layer boards can be considered. Both solutions can improve the performance of EMI suppression, but they are only suitable for occasions where the component density on the board is low enough and there is enough area around the components (to place the required power copper layer).

The first is the preferred solution. The outer layers of the PCB are all ground layers, and the two middle layers are signal/power layers. The power supply on the signal layer is routed with wide lines, which can make the path impedance of the power supply current low and the impedance of the signal microstrip path low. From the perspective of EMI control, this is the best 4-layer PCB structure available. The second solution uses power and ground on the outer layers and signals on the middle two layers. This solution is less improved than the traditional 4-layer board, and the inter-layer impedance is as poor as the traditional 4-layer board.

If the routing impedance is to be controlled, the above stacking solutions must be very careful to arrange the routing under the power and ground copper islands. In addition, the copper islands on the power or ground layers should be interconnected as much as possible to ensure DC and low-frequency connectivity.

6-layer board

If the component density on the 4-layer board is relatively large, it is best to use a 6-layer board. However, some stacking schemes in the 6-layer board design do not have a good shielding effect on the electromagnetic field and have little effect on reducing the transient signal of the power bus. Two examples are discussed below.

In the first example, the power supply and ground are placed on the 2nd and 5th layers respectively. Due to the high impedance of the power copper, it is very unfavorable to control the common mode EMI radiation. However, from the perspective of signal impedance control, this method is very correct.

In the second example, the power supply and ground are placed on the 3rd and 4th layers respectively. This design solves the problem of power copper impedance. Due to the poor electromagnetic shielding performance of the 1st and 6th layers, the differential mode EMI increases. If the number of signal lines on the two outer layers is the least and the routing length is very short (shorter than 1/20 of the wavelength of the highest harmonic of the signal), this design can solve the differential mode EMI problem. Filling the component-free and routing-free areas on the outer layer with copper and grounding the copper area (at intervals of 1/20 wavelength) will have a particularly good suppression of differential mode EMI. As mentioned earlier, the copper area should be connected to the internal ground layer at multiple points.

General high-performance 6-layer board design Generally, the 1st and 6th layers are laid as ground layers, and the 3rd and 4th layers are used for power and ground. Since there are two layers of dual microstrip signal lines in the middle between the power layer and the ground layer, the EMI suppression capability is excellent. The disadvantage of this design is that there are only two routing layers. As mentioned earlier, if the outer layer routing is short and copper is laid in the non-routing area, the same stacking can be achieved with a traditional 6-layer board.

Another 6-layer board layout is signal, ground, signal, power, ground, signal, which can achieve the environment required for advanced signal integrity design. The signal layer is adjacent to the ground layer, and the power layer and the ground layer are paired. Obviously, the disadvantage is that the stacking of the layers is unbalanced.

This usually brings trouble to processing and manufacturing. The solution to the problem is to fill all the blank areas of the 3rd layer with copper. After copper filling, if the copper density of the 3rd layer is close to that of the power layer or the ground layer, this board can be loosely regarded as a structurally balanced circuit board. The copper-filled area must be connected to the power supply or ground. The distance between the connecting vias is still 1/20 wavelength. It is not necessary to connect everywhere, but ideally it should be connected.

10-layer board

Since the insulation isolation layer between multi-layer boards is very thin, the impedance between layers of 10 or 12-layer circuit boards is very low. As long as there is no problem with layering and stacking, excellent signal integrity can be expected. It is difficult to manufacture 12-layer boards with a thickness of 62mil, and there are not many manufacturers who can process 12-layer boards.

Since there is always an insulation layer between the signal layer and the loop layer, it is not the best to allocate the middle 6 layers to route the signal line in the 10-layer board design. In addition, it is important to make the signal layer adjacent to the loop layer, that is, the board layout is signal, ground, signal, signal, power, ground, signal, signal, ground, signal.

This design provides a good path for signal current and its loop current.

The appropriate wiring strategy is to route the first layer in the X direction, the third layer in the Y direction, the fourth layer in the X direction, and so on. Intuitively looking at the routing, Layer 1 and Layer 3 are a pair of layer combinations, Layer 4 and Layer 7 are a pair of layer combinations, and Layer 8 and Layer 10 are the last pair of layer combinations. When the routing direction needs to be changed, the signal line on Layer 1 should go to Layer 3 through “vias” before changing direction. In practice, this may not always be possible, but as a design concept, it should be followed as much as possible.

Similarly, when the routing direction of the signal changes, it should go from Layer 8 and Layer 10 or from Layer 4 to Layer 7 through vias. This routing ensures the tightest coupling between the forward path and the loop of the signal. For example, if the signal is routed on Layer 1, and the loop is on Layer 2 and only on Layer 2, then even if the signal on Layer 1 is transferred to Layer 3 through “vias”, its loop is still on Layer 2, thereby maintaining the characteristics of low inductance, large capacitance, and good electromagnetic shielding performance.

What if the actual routing is not like this?

For example, if the signal line on the first layer goes to the tenth layer through a via, the loop signal has to find the ground plane from the ninth layer, and the loop current has to find the nearest ground via (such as the ground pin of a resistor or capacitor). If such a via happens to exist nearby, you are really lucky. If there is no such via available, the inductance will increase, the capacitance will decrease, and EMI will definitely increase.