Key points and related guidelines for designing PCBs using high-speed FPGAs

In circuit board design, in order to minimize crosstalk, the routing of microstrip and stripline can follow several guidelines. For dual-strip layouts, the routing is performed on two inner layers, and there is a voltage reference plane on both sides. At this time, it is best to use orthogonal routing technology for all adjacent layer conductors, maximize the thickness of the dielectric material between the two signal layers, and minimize the distance between each signal layer and its adjacent reference plane, while maintaining the required impedance.

Guidelines for microstrip or stripline routing

The trace spacing is at least three times the thickness of the dielectric layer between the circuit board routing layers; it is best to use simulation tools to simulate its behavior in advance.

Use differential instead of single-ended topology for critical high-speed networks to minimize the impact of common-mode noise. Within the design limits, try to match the positive and negative pins of the differential signal path.

Reduce the coupling effect of single-ended signals, leave appropriate spacing (greater than three times the trace width), or route on different board layers (adjacent layer routing is orthogonal to each other). In addition, using simulation tools is also a good way to meet spacing requirements.

Minimize the parallel length between signal terminations.

Simultaneous Transition Noise

As clock and I/O data rates increase, the number of output transitions decreases, and transient currents increase during the discharge and recharge of signal paths. These currents can cause board-level ground bounce, which is a momentary rise/fall in ground voltage/Vcc. Large transient currents from non-ideal power supplies can cause momentary drops in Vcc (Vcc dips or sags). Here are a few good board design rules to help reduce the effects of these simultaneous transition noises.

The figure shows the recommended number of signal, power, and ground planes when the available I/Os are fully utilized.

Configure unused I/O pins as output pins and drive them at low voltages to reduce ground bounce.

Minimize the number of output pins that switch simultaneously and distribute them evenly throughout the FPGA I/O section.

When high edge rates are not required, use low slew rates for FPGA outputs.

Place Vcc between ground planes on multilayer boards to eliminate the effects of high-speed traces on each layer.

Dedicating entire board layers for Vcc and ground minimizes the resistance and inductance of these planes, providing a low-inductance source with lower capacitance and noise, and returning logic signals on signal layers adjacent to these planes.

Pre-emphasis, equalization

The high-speed transceiver capabilities of state-of-the-art FPGAs make them highly effective programmable system-on-chip components, but also present unique challenges for board designers. A key issue, especially with respect to layout, is frequency-dependent transmission losses, primarily caused by skin effect and dielectric losses. When high-frequency signals are transmitted over the surface of a conductor (such as a PCB trace), skin effect occurs due to the self-inductance of the conductor. This effect reduces the effective conducting area of ​​the conductor, attenuating the high-frequency components of the signal. Dielectric losses are caused by the capacitive effects of the dielectric material between the board layers. The skin effect is proportional to the square root of the frequency, while dielectric losses are proportional to the frequency; therefore, dielectric losses are the dominant loss mechanism for attenuating high-frequency signals.

The higher the data rate, the more severe the skin effect and dielectric losses become.

For 1Gbps systems, the reduction in signal levels on the link is acceptable, but it is not acceptable for 6Gbps systems. However, today’s transceivers have transmitter pre-emphasis and receiver equalization functions to compensate for distortion in high-frequency channels. They also enhance signal integrity and relax trace length restrictions. These signal conditioning techniques extend the life of standard FR-4 materials and support higher data rates. Due to signal attenuation in FR-4 materials, the allowable trace length is limited to a few inches when operating at a rate of 6.375Gbps. Pre-emphasis and equalization can extend this to more than 40 inches.

Programmable pre-emphasis and equalization are integrated in some high-performance FPGAs, such as Stratix II GX devices, so they can use FR-4 materials and relax layout restrictions such as maximum trace length, reducing board costs.

Pre-emphasis can effectively boost the high-frequency components of the signal. The 4-tap pre-emphasis circuit in Stratix II GX can reduce the scattering of signal components (the space from one bit to another). The pre-emphasis circuitry provides up to 500% pre-emphasis, with each tap being optimized up to 16 levels depending on data rate, trace length, and link characteristics.

The Stratix II GX receiver includes a gain stage and linear equalizer to compensate for signal attenuation.

In addition to the input gain stage, the device also gives board designers equalization levels up to 17 dB, using any of 16 equalizer stages to overcome board loss issues. The equalization and pre-emphasis features can be used in concert environments or to optimize specific links individually.

Designers can change the pre-emphasis and equalization levels in the Stratix II GX FPGA while the system is running, or during card configuration after it is inserted into a backplane or other chassis. This gives system designers the flexibility to automatically set the pre-emphasis and equalization levels to predetermined values. Alternatively, these values ​​can be dynamically determined based on which slot in the chassis or backplane the board is inserted into.

EMI Issues and Debugging

The electromagnetic interference caused by a printed circuit board is directly proportional to the change in current or voltage over time, as well as the series inductance of the circuit. Effective board design can minimize EMI, but not necessarily eliminate it. Eliminating “aggressor” or “hot” signals and routing signals with proper reference to the ground plane can also help reduce EMI. Finally, using surface mount components, which are common in today’s market, is also a way to reduce EMI.

Debugging and testing complex high-speed PCB designs has become increasingly difficult because some traditional board debugging methods, such as test probes and “Bed-of-nails” testers, may not be applicable to these designs. These new high-speed designs can take advantage of JTAG test tools with in-system programming capabilities and built-in self-test capabilities that FPGAs may have. Designers should use the same guidelines to set the JTAG test clock input (TCK) signal as the system clock. It is also important to minimize the length of the JTAG scan chain trace between the test data output of one device and the test data input of another device.

Successful design with embedded high-speed FPGAs requires ample high-speed board design practice and a good understanding of FPGA capabilities, such as pinouts, board materials and stack-up, board layout, and termination patterns. Proper use of the pre-emphasis and equalization features of the built-in transceiver is also important. The above points combine to achieve a reliable design with stable manufacturability. Careful consideration of all these factors, coupled with correct simulation and analysis, can minimize the possibility of unexpected events in the circuit board prototype and help reduce the stress of the circuit board development project.