Using parameter constraints for PCB design
Today, PCB design considers more and more complex factors, such as clock, crosstalk, impedance, detection, manufacturing process, etc., which often requires designers to repeat a lot of layout, routing, verification and maintenance work. The parameter constraint editor can compile these parameters into formulas to help designers better handle these sometimes even conflicting parameters during the design and production process.
In recent years, the requirements for PCB layout and routing have become more and more complex.
The number of transistors in integrated circuits is still increasing at the rate predicted by Moore’s law, making the device faster and the rise time of each pulse edge shorter. At the same time, the number of pins is increasing – often to 500 to 2,000 pins. All of this will bring problems such as density, clock and crosstalk when designing PCBs.
A few years ago, most PCBs had only a few “critical” nodes (nets), usually referring to some constraints in impedance, length and spacing.
PCB designers generally manually routed these traces first, and then used software to automatically route the entire circuit on a large scale. Today’s PCBs often have 5,000 or even more nodes, and more than 50% of them are critical nodes. Due to time-to-market pressures, manual routing is no longer possible. In addition, not only has the number of critical nodes increased, but the constraints on each node have also increased.
These constraints are mainly due to parameter dependencies and increasingly complex design requirements.
For example, the spacing between two traces may depend on a function related to both node voltage and circuit board material. The reduction in digital IC rise time affects both high- and low-clock speed designs. The setup and hold times are shorter due to faster pulse generation. In addition, interconnect delay, as an important part of the total delay of high-speed circuit design, is also very important for low-speed design.
If the circuit board can be designed larger, some of the above problems will be easier to solve, but the current development trend is just the opposite. Due to the requirements on interconnect delay and high-density packaging, circuit boards are becoming smaller and smaller, resulting in high-density circuit design, and miniaturization design rules must be followed. The reduction in rise time coupled with these miniaturization design rules makes crosstalk noise problems more and more prominent, and ball grid arrays and other high-density packaging themselves will also aggravate crosstalk, switching noise and ground bounce problems.
Limitations of fixed constraints
The traditional approach to dealing with these problems is to convert electrical and process requirements into fixed constraint parameters based on experience, default values, tables or calculation methods. For example, when designing a circuit, an engineer may first determine a rated impedance, and then “estimate” a rated line width that can achieve the required impedance based on the final process requirements, or use a calculation table or arithmetic program to test interference and then find the length constraint.
This method usually requires the design of a set of empirical data as a basic guideline for PCB designers so that these data can be used when designing with automatic layout and routing tools. The problem with this method is that empirical data is only a general principle. In most cases, they are correct, but sometimes they do not work or lead to wrong results.
Let’s take the example of determining impedance above to see the errors that may be caused by this method. Factors related to impedance include the dielectric properties of the circuit board material, the height of the copper foil, the distance between each layer and the ground/power layer, and the line width. Since the first three parameters are generally determined by the production process, designers usually rely on line width to control impedance.
Since the distance from each line layer to the ground or power layer is different, it is obviously wrong to use the same empirical data for each layer. In addition, the production process or circuit board characteristics used in the development process may change at any time, so the problem will be further complicated.
Most of the time, these problems are exposed in the prototype production stage, and they are generally solved by repairing the circuit board or redesigning the board after the problem is found. This is relatively expensive, and repairs often bring additional problems that require further debugging. In the end, the loss of revenue caused by delayed time to market is far greater than the debugging cost. Almost every electronics manufacturer faces this problem, and it ultimately comes down to the fact that traditional PCB design software cannot keep up with the actual situation of current electrical performance requirements, which is not as simple as the empirical data of mechanical design.
Solution: Parameterized constraints
Currently, design software vendors are trying to solve this problem by adding parameters to the constraints. The most advanced part of this method is that it can detail mechanical indicators that fully reflect various internal electrical characteristics. Once it is added to the PCB design, the design software can use this information to control the automatic layout and routing tools.
When Designers only need to simply update the process characteristic parameters to automatically change the relevant constraints.
Designers can then run a DRC (design rule check) to determine if the new process violates other design rules and find out what aspects of the design should be changed to correct any errors.
Constraints can be entered as mathematical expressions, containing constants, various operators, vectors, and other design constraints, providing designers with a parameterized rule-driven system. Constraints can even be entered as lookup tables, which are stored in the design file of the PCB or schematic. PCB routing, copper foil area location, and layout tools all follow the constraint rules generated by these conditions, and DRC verifies whether the entire design meets these constraints, including line width, spacing, and space requirements (such as area and height restrictions).
A very simple example is the rise time constraint, which is generally set to a constant of 1.5ns.
Based on this condition, the maximum trace length constraint can be obtained, that is, 5,800mil/ns multiplied by the rise time of 1.5ns. A slightly more complex example is the component spacing, which is determined by multiplying the tangent of the detection angle by the device height. This formula can calculate the minimum component spacing value.
Hierarchical management
One of the main benefits of parametric constraints is that they can be processed hierarchically. For example, the global line width rule can be used as a design constraint for the entire design. Of course, there will be individual areas or nodes that cannot follow this principle. At this time, the higher-level constraints can be bypassed and the lower-level constraints in the hierarchical design can be used. Taking ACCEL Technologies’ constraint editor Parametric Constraint Solver as an example, there are 7 levels of constraints:
- Design constraints, used for all objects without other constraints.
- Hierarchical constraints, used for objects on a certain layer.
- Node type constraints, used for all nodes contained in a certain type.
- Node constraints, used for a certain node.
- Inter-class constraints, representing constraints between two types of nodes.
- Space constraints, used for all devices in a certain space.
- Device constraints, used for a certain device.
The software follows each design constraint in order from individual devices to the entire design rules, and graphically displays the order in which these rules are applied in the design.
·Example 1: Line width = f(impedance, layer spacing, dielectric constant, copper foil height)
Here is an example to illustrate how parameterized constraints can be used as design rules to control impedance. As mentioned earlier, impedance is a function of dielectric constant, distance to the nearest circuit layer, copper wire width and height. Since the impedance required by the design has been determined, these four parameters can be arbitrarily taken as related variables to rewrite the impedance formula. In most cases, the only parameter that designers can control is line width.
Because of this, the constraint on line width is a function of impedance, dielectric constant, distance to the nearest circuit layer, and copper foil height. If the formula is defined as a hierarchical constraint and the manufacturing process parameters are defined as design-level constraints, the software will automatically adjust the line width to compensate when the designed circuit layer changes. Similarly, if the designed circuit board is produced using another process and the copper foil height changes, the relevant rules in the hierarchy can be automatically recalculated by simply changing the copper foil height parameter in the design level.
·Example 2: Device spacing = max(default spacing, f(device height, detection angle))
The obvious benefit of using parameter constraints and design rule checking at the same time is that the parameterized method has good portability and monitorability when the design is modified. This example shows how the device spacing is determined by process characteristics and test requirements. The above formula shows that the device spacing is a function of device height and detection angle.
Usually the detection angle is a constant for the entire board, so it can be defined at the design level. When the inspection is changed to a different machine, the entire design can be updated by simply entering the new value at the design level. After entering the new machine performance parameters, the designer can simply run the DRC to check whether the device spacing conflicts with the new spacing value to know whether the design is feasible, which is much easier than analyzing and correcting it first and then calculating it hard according to the new spacing requirements.
·Example 3: Component layout
In addition to organizing design objects and constraints, design rules can also be used for component layout, that is, it can detect where to place components without errors based on constraints. The highlighted part in Figure 1 is the device placement area that meets physical constraints (such as spacing from the board edge and device spacing, etc.), Figure 2 highlights the device placement area that meets electrical constraints, such as maximum trace length, Figure 3 only shows the area that meets space constraints, and finally, Figure 4 is the intersection of the parts in the first three figures, which is the effective layout area, and the devices placed in this area can meet all constraints.
In fact, generating constraints in a modular way can greatly improve their maintainability and reusability. New expressions can be generated by referring to the constraint parameters of different layers in the previous stage, such as the top layer line width depends on the distance and copper line height of the top layer and the variables Temp and Diel_Const in the design level. Please note that the design rules are displayed in order from low to high, and changing a higher level constraint will immediately affect all expressions that refer to this constraint.
Design Reuse and Documentation
Parameterized constraints can not only significantly improve the initial design process, but also make it more useful for engineering changes and design reuse. Constraints can be part of the design, system and documentation. If they are not stored in the minds of engineers or designers, they may be slowly forgotten when they move to other projects. Constraint documents record the electrical performance rules that should be followed during the design process, giving others the opportunity to understand the designer’s intentions, making it easy to apply these rules to new manufacturing processes or change them according to electrical performance requirements. Future reusers can also know the exact design rules and make changes by entering new process requirements, without having to guess questions such as how the line width is obtained.
Conclusion of this article
The parameter constraint editor facilitates PCB layout and routing under multi-dimensional constraints. This is also the first time that automatic routing software and design rules can be checked completely according to complex electrical and process requirements, rather than relying solely on experience or simple and useless design rules. The result is that the design can be successful at the first time, reducing or even eliminating prototype debugging.
