3G network and PCB signal integrity issues
Signal integrity issues
1.Definition of signal integrity
Signal integrity (SignalIntegrity) refers to a state in which the signal is not damaged. It indicates that the signal still maintains its correct functional characteristics after being transmitted through the signal line, and the signal can respond with the correct timing and voltage in the circuit.
From the timing of the IC, it can be seen that if the signal has a large jump during the steady-state time (in order to correctly identify and process data, the IC requires the input data to remain unchanged before and after the clock edge), the IC may misjudge or lose part of the data. If the signal has good signal integrity, the circuit has the correct timing relationship and signal amplitude, and the data will not be captured incorrectly, which means that the receiving end can obtain relatively pure data.
On the contrary, if there are signal integrity failures such as false triggering, damped oscillation, overshoot, and undershoot, it will cause arbitrary signal jumps, resulting in the input distorted data being sent to the latch, or capturing data at the distorted clock jump edge, and the signal cannot respond normally, resulting in abnormal system operation and performance degradation. Figure 2 shows the simulation results of signal integrity.
2.Causes and manifestations of signal integrity
Signal integrity originates from the interconnection of circuits (such as wires, substrates, and wells). Since a section of wire is not just a conductor of electrons, it is resistive in the low frequency band, capacitive in the mid-frequency band, inductive in the high frequency band, and becomes a radiating antenna at very high frequencies. It is this antenna effect that causes signal crosstalk and electromagnetic interference (EMI).
Since the interaction between carriers and atoms and grains in the conductor generates resistance, as the characteristic size is compressed to below 0.5μm, the skin effect causes the metal surface resistance to decrease more slowly than the cross-sectional resistance, causing signal integrity damage.
The capacitive effect caused by the structure of independent voltages that are too close increases as the wiring spacing decreases, which has a greater potential impact on the transmission characteristics of the signal. The inductance effect determined by the lead size and return path becomes the main concern of packaging and circuit board design. When the IC size is less than 0.5μm, the inductance effect becomes very obvious.
There will be obvious mutual inductance between two parallel traces, and some noise will be coupled into the logic circuit, causing the signal to present a phenomenon that is completely different from that in low-frequency design. The ability of digital systems to tolerate signal integrity problems is limited. When signal integrity problems reach a certain level, the system performance may be degraded or even not work at all. Simulation test results confirm that excessive IC switching speed, improper layout of terminal components, and unreasonable circuit interconnection can all cause signal integrity problems. Signal integrity mainly includes reflection, crosstalk, oscillation, ground bounce, etc.
Signal reflection
Signal reflection (reflection) is the echo on the transmission line. Part of the signal power is transmitted to the load through the transmission line, and the other part is reflected to the source end. In high-speed design, the wire can be equivalent to a transmission line instead of a wire in a concentrated parameter circuit. By examining its impedance at different frequencies, its transmission effect can be studied. If the edge rate is as high as 1V/ns (i.e. dV/dt), a wire shorter than 0.5 inches can be built into a T-type concentrated parameter RLC (or RC, LC) model, and multiple T-type cascades can be combined into a longer transmission line. In order to reduce the amount of simulation calculations, a continuous transmission line model can also be established. If the impedance is matched (the source impedance, transmission line impedance and load impedance are equal), reflection will not occur. Conversely, if the load impedance and the transmission line impedance are mismatched, it will cause end reflection. The geometry of the wiring, improper termination, transmission through the connector, and discontinuity of the power plane can all cause signal reflection.
Signal overshoot and undershoot
Signal overshoot refers to the first peak (or valley) of the signal transition exceeding the specified value-for the rising edge, it refers to the highest voltage, and for the falling edge, it refers to the lowest voltage. Undershoot refers to the next valley (or peak) of the signal transition. Signal overshoot and undershoot are caused by the high switching rate of the IC and the reflection of the signal transmission path. Multiple reflections between the driver and the receiver will form damped oscillations. If the oscillation amplitude exceeds the input switching threshold of the IC, it will cause clock errors or erroneous reception of data. Excessive overshoot may also cause overvoltage or even damage to the components inside the IC.
Signal crosstalk
Signal crosstalk (cross-talk) is the electromagnetic coupling phenomenon caused by the induced voltage and induced current between signal lines that are not electrically connected. This coupling makes the signal line act as an antenna. Its capacitive coupling induces coupling current, and inductive coupling induces coupling voltage. It increases with the increase of clock speed (leading to increased edge rate) and the reduction of design size. This is because when the alternating signal current passes through the signal line, an alternating magnetic field is generated, and other signal lines in the magnetic field will induce signal voltage. In the low frequency band, the coupling between the wires can be established as a coupling capacitor model, and in the high frequency band, it can be established as an LC concentrated parameter wire or transmission line model. The parameters of the PCB board layer, the spacing between the signal lines, the electrical characteristics of the driving end and the receiving end, and the termination method of the signal line have a certain impact on crosstalk.
Electromagnetic interference
Electromagnetic interference is similar to signal crosstalk. Signal crosstalk is the coupling between two transmission lines on the PCB, and electromagnetic interference is the interference of the transmission line on the PCB by the radiation source outside the PCB (such as test probes or other PCB boards). EMI modeling can treat the wire segment as a dipole antenna.
Signal oscillation and rounding
Signal oscillation (ringing) and rounding (rounding) are manifested as repeated overshoot and undershoot of the signal, jittering above and below the threshold of the logic level, oscillation in an underdamped state, and rounding in an overdamped state. Signal oscillation and rounding are mainly caused by excessive parasitic inductance and capacitance on the transmission line, which causes mismatch between the receiving end impedance and the source end. Like reflection, they can be suppressed by proper termination. Usually, periodic pulse signals contain abundant high-order harmonics and are prone to signal integrity failures, such as clock signals, which should be more guarded against.
Signal delay
Signal delay indicates that the data or clock signal does not reach the receiving end within the specified time with a certain duration and amplitude. IC can only receive data according to the specified timing. Excessive signal delay may cause timing violation and functional confusion. Signal delay is caused by the transmission line effect of overloaded drive and long routing. The equivalent capacitance and inductance on the transmission line will cause delay in the digital switching of the signal, affecting the setup time and hold time of the IC. If the delay is too large, the IC will not be able to correctly judge the data.
Ground bounce and substrate coupling
Ground bounce, also known as ground bounce, refers to the phenomenon that a large amount of noise is generated between the power supply and the ground plane due to a large current surge in the circuit. For example, when a large number of chips are switched synchronously, a large transient current will flow through the chip and the power plane. The parasitic inductance, capacitance and resistance between the chip package and the power supply will cause power supply noise, resulting in a large voltage fluctuation (possibly up to 2V) on the zero potential plane, which is enough to cause erroneous operation of other components. Due to the division of the ground plane (digital ground, analog ground, shielding ground, etc.), the ground plane may rebound when the digital signal goes to the analog ground area. The same power plane division may also cause the same harm. The increase in load capacitance, the decrease in resistance, the increase in parasitic parameters, the increase in switching rate and the increase in the number of synchronous switching may all lead to an increase in ground bounce.
At the same time, substrate coupling may make the design face greater challenges. In silicon wafer design, since the substrate and well have limited resistivity, a certain voltage drop will be generated when current flows through them. The threshold voltage (turn-on) of the MOSFET depends on the effective voltage of the substrate (or well) below the gate region, which means that any substrate current can not only cross the threshold voltage of the MOSFET, but also the threshold voltage of the logic gate or clock circuit, making the design very unreliable. As the horizontal and vertical scales decrease, the resistance of the substrate and well layers increases, and the situation becomes worse.
Solutions to signal integrity
For chip design, two methods are usually used to solve signal integrity problems. Its RF solution focuses on transmission lines and often uses impedance matching methods on the package boundary, while the digital (i.e. broadband) solution emphasizes the selection of packages, controlling the number and speed of simultaneous switching, using bypass capacitors between the external power pins of the package and the ground, and the capacitors inside the IC are realized by overlapping metal layers, that is, providing a local low-impedance path for high-speed transient currents to prevent ground bounce.
However, when faced with signal integrity problems in deep submicron designs, the usual solutions are no longer applicable.
For example, although limiting the edge rate (Slew rate) can significantly improve ground bounce and crosstalk, it also limits the clock rate. Research on new solutions must be suitable for deep submicron IC design. For example, the problem of increasing substrate resistance can be solved by using silicon-on-insulator technology (SOI), which is a technology widely used in micron IC design. Now, the main methods to solve signal integrity problems are circuit design, reasonable layout and modeling simulation.
1.Circuit design
In the circuit design process, the number of synchronous switching outputs is controlled by design, and the maximum edge rate (dI/dt and dV/dt) of each unit is controlled to obtain the lowest and acceptable edge rate, which can effectively control the integrity of the signal. Differential signals can also be selected for high-output functional blocks (such as clock drivers). For example, the clock usually uses ECL signals or full-swing differential signals. For application engineers, passive components (resistors, capacitors and ferrites) are usually terminated on the transmission line to achieve impedance matching between the transmission line and the load. The choice of termination strategy should be a compromise between the increase in the number of components, switching speed and power consumption. The termination series resistor R or RC circuit should be as close to the excitation end or the receiving end as possible, and impedance matching should be obtained. At the same time, the resistor R (such as 10Ω) can consume the useless DC power of the logic circuit, and the capacitor (such as 39PF) can weaken the damping oscillation strength under the condition of meeting the switching speed, but the capacitor must be carefully selected to prevent oscillation (ringing) caused by its pin inductance.
2.Reasonable wiring
Wiring is very important. Designers should use existing design experience, integrate multiple possible solutions, optimize wiring, and eliminate various potential problems without violating general principles. Although there are some design rule-driven wiring machines that help designers optimize designs, there is no wiring machine that fully customizes design rules by users and fully supports signal integrity analysis. Wiring tools should be combined with all parasitic parameter extraction to obtain accurate predictions of hysteresis rate and delay. A successful wiring machine should not only have accurate parasitic parameter extraction, but also be combined with signal integrity tools. When it is found that the signal integrity drops below the required threshold, it can cut the wire and rewire.
3.Modeling and simulation
Reasonable circuit modeling and simulation is the most common solution. In modern high-speed circuit design, simulation analysis shows its superiority. It gives designers accurate and intuitive design results, which facilitates early detection of hidden dangers, timely modification, shortening design time and reducing design costs. Designers should make reasonable estimates of relevant factors and establish reasonable models. For IC design, circuit simulation must be carried out in a packaged environment so that the simulation results can be closer to the test results of silicon wafers returned after molding. Since signal integrity problems often appear as intermittent errors, it is important to pay attention to synchronous switching control, simulation and packaging to ensure that the design meets the signal integrity requirements and solve the problem before silicon wafer manufacturing. For IC applications, simulation can be used to select reasonable termination components and optimize the layout of components, making it easier to identify potential problems and promptly adopt the correct termination strategy and layout constraint mechanism to solve related signal integrity problems. With the increase in clock frequency and the continuous decrease in IC size, maintaining signal integrity is becoming more and more challenging for designers, which makes modeling and simulation an indispensable part of design.
Introduction to signal integrity simulation models and tools
Nowadays, there are many simulation tools used to analyze signal integrity, each with its own characteristics, which can be appropriately selected.
1 SPICE model
The SPICE (Simulation Program with Integrated Circuit Emphasis) model was developed the earliest and has become an informal standard for analog transistor circuit description in the IC industry. It is based on the modeling of transistor and diode characteristic parameters, so the amount of calculation is very large and the calculation is extremely time-consuming (maybe several days), so users need to compromise between simulation accuracy and calculation time. SPICE models generally do not support the simulation of coupled lines (or loss lines), which is the key factor in signal integrity simulation in high-speed circuit design.
2 IBIS model
The IBIS (Input/Output Buffer Information Specification) model is an international standard that reflects the chip driving and receiving electrical characteristics. It is based on the V/I curve and quickly models the I/O BUFFER. It provides a standard file format to record parameters such as excitation source output impedance, rise/fall time and input load, which is very suitable for system-level calculation and simulation of high-frequency effects such as oscillation and crosstalk. IBIS is a simple model with small calculation amount, fast speed and high accuracy, and has been widely adopted.
3 VHDL-AMS
VHDL-AMS is a modeling language for analog and mixed signal behavior. It uses analog equations and digital VHDL to describe circuit functions. It is a relatively new standard and does not have a broad model developer base and is not supported by many simulators. Before it is widely used for signal integrity simulation, a lot of work needs to be done by the model simulator developer.
4 Quantic EMC
Quantic EMC is a signal integrity and EMC software simulation analysis tool. It is a dedicated EMC analysis tool for Siemens. Its OmegaPLUS is the software that Quantic EMC runs on a PC. It uses the VI model of the device to easily simulate signal integrity and EMI. It is powerful and efficient.
5 XTK
XTK is a high-performance signal integrity analysis tool developed by Viewlogic in the field of high-speed system design HSSD (High Speed System Design). It can accurately analyze the signal quality and transmission line delay of complex PCBs, MCMs and systems composed of multiple PCB boards. XTK is a crosstalk analysis toolkit that contains a variety of analysis tools.
6 LineSim and BoardSim
LineSim and BoardSim are simulation tools developed by HyperLynx (a subsidiary of PADS Software). LineSim is used to constrain routing and layer parameters, set clock routing topology, select component speed, diagnose and avoid signal integrity, electromagnetic radiation and crosstalk issues before routing. BoardSim is used to quickly analyze the circuit after routing.Analyze signal integrity, electromagnetic compatibility, and crosstalk issues in your design, generate crosstalk strength reports, and identify and resolve crosstalk issues.
