Top 10 Tips to Improve IP Verification Efficiency

Functional verification is becoming a bottleneck in IP verification and affects the entire design team. Design engineers seek ways to improve verification efficiency to achieve the best benefits for the entire chip design. Here, we provide 10 simple tips to significantly improve your IP verification efficiency.

1.Participate in verification plan review

Well begun is half done! Investing in a validation plan is very important. Many times, a verification plan without clear microarchitectural documentation is incomplete (from a white-box verification point of view). Initial investment can reduce many obstacles in implementation. You need to prioritize based on your design and development plan. You also need to be invested in the integrity of your validation plan. Additionally, if your verification team is planning to purchase third-party verification IP, make sure it meets the specific customization requirements of the DUT.

2.Document interface signals, registers, and data flows

Documentation is a luxury! Many design engineers follow the philosophy that “code is documentation”. This is understandable, since you are fighting against time. However, basic documentation and basic data flow information about the interface between the test device and the testbench can go a long way in improving verification efficiency. These documents can serve as a reference throughout the debugging process to avoid confusion.

3.Complete the top-level compilation of DUT before system integration
In order to deliver the RTL to the verification team earlier,

engineers often skip the RTL top-level compilation of the DUT. You must not ignore this step. Every newly written testbench will have its own problems. Referencing an immature DUT will only complicate the problem. Therefore, it is best to provide the verification team with a DUT top-level RTL coding without errors as a reference.

4.Avoid dangle signals on the top layer of the DUT
The dangle signal is a connection signal between internal modules.

However, due to missing connections, these dangle signals will end up on ports at the top level. This broke the testbench toplevel compilation causing confusion. You need to connect them internally and deliver the top level of the DUT as per the specification with reference to the predefined port list.

5.Add necessary assertions for key assumptions and interface signals
Assertions are becoming more and more popular,

it would be beneficial if you could spend a little more effort to add the necessary assertions. This can be a simple internal FIFO empty or full assertion, or a more complex assertion based on assumptions about any input stimulus or any exceptions that may occur. Assertions on interface signals on the DUT can provide timely information to determine whether verification engineers have correctly integrated the DUT. These early assertions can save a lot of time in later debugging.

6.Bypassing lengthy initialization sequences

Many interface protocol specifications enumerate long initialization sequences to provide configuration flexibility. After some initial testing, the focus of verification will shift to other aspects. Most tests are intended to verify features outside of the initialization sequence, so you should provide ways to bypass these long initialization sequences.

7.Set a variable timer duration

Designs often use timers to avoid hang situations. These timers are either compliant with the standard specification or are internally defined. Typically, these timers are set to very long values ​​to prevent them from timing out. However, testing those very long values ​​would require a lot of simulation time. Some values ​​are even unattainable by simulation tests. So, you need to make your timer scalable to ensure that the timer can scale effortlessly. At the same time, you should also adjust other related configurations to make sure the timer can simulate smoothly.

8.Consistency Verification

This step is the “icing on the cake”! With the increasing popularity of formal verification tools, designers can do some conformance verification without investing heavily in testbenches. Performing some very basic testing of the design (or major blocks of the design) will save a lot of time, thus accelerating the start of comprehensive verification.

9.Use System Verilog interface at the top level of DUT

Designers love Verilog, but most verification in the world today is done with System Verilog. You should gradually explore the “design-friendly” features of System Verilog. Provide a System Verilog interface to the top level of the DUT instead of a list of Verilog ports. This can be a good start in reducing integration time and also provides a suitable place for interface assertions. Furthermore, this will help transform the design thinking process from pure Verilog to System Verilog – which is undoubtedly beneficial in the long run.

10.Participate in functional coverage convergence

You could say, “I already handled code coverage convergence. Functional coverage convergence is none of my business.” That’s right. However, delayed verification convergence is bound to cost you more effort in the long run. Bugs fixed late in timing-critical design areas can lead to rework for timing closure (a very painful process). Therefore, it is best for you to participate and guide the convergence of functional coverage throughout the process, especially the key or weak links.