Signal return and cross-segmentation in high-speed PCB

Here is a simple “scenario” to introduce ground return and power return and some cross-segmentation issues in combination with the following figure. For the convenience of drawing, the layer spacing is enlarged.

IC1 is the signal output end, IC2 is the signal input end (to simplify the PCB model, it is assumed that the receiving end contains a bottom connection resistor) and the third layer is the ground layer. The ground of IC1 and IC2 both come from the third layer ground layer. The upper right corner of the top layer is a power plane connected to the positive pole of the power supply. C1 and C2 are decoupling capacitors for IC1 and IC2 respectively. The power supply and ground pins of the chip shown in the figure are the power supply and ground of the transmitting and receiving signal ends.

At low frequencies, if the S1 end outputs a high level, the entire current loop is that the power supply is connected to the VCC power plane through the wire, then enters IC1 through the orange path, then comes out from the S1 end, enters IC2 along the second layer of wires through the R1 end, then enters the GND layer, and returns to the negative pole of the power supply through the red path.

But at high frequencies, the distribution characteristics presented by the PCB will have a great impact on the signal.

The ground return current we often talk about is a problem that is often encountered in high-frequency signals. When there is an increased current in the signal line from S1 to R1, the external magnetic field changes rapidly, causing the nearby conductor to induce a reverse current. If the ground plane of the third layer is a complete ground plane, there will be a current marked by a blue dotted line on the ground plane; if the TOP layer has a complete power plane, there will also be a return along the blue dotted line on the top layer. At this time, the signal loop has the smallest current loop, the energy radiated outward is the smallest, and the ability to couple external signals is also the smallest. (The skin effect at high frequencies also radiates the least energy outward, and the principle is the same.)

Since the high-frequency signal level and current change very quickly, but the change cycle is short, the energy required is not very large, so the chip is powered by the decoupling capacitor closest to the chip. When C1 is large enough and the reaction is fast enough (with a very low ESR value, usually ceramic capacitors are used. The ESR of ceramic capacitors is much lower than that of tantalum capacitors.), the orange path on the top layer and the red path on the GND layer can be regarded as non-existent (there is a current corresponding to the power supply of the entire board, but not the current corresponding to the signal shown in the figure).

Therefore, according to the environment constructed in the figure, the entire path of the current is:

positive pole of C1->VCC of IC1->S1->L2 signal line->R1->GND of IC2->via->yellow path of GND layer->via->negative pole of capacitor.

It can be seen that there is a brown equivalent current in the vertical direction of the current, and a magnetic field will be induced in the middle. At the same time, this ring surface can also easily couple to external interference. If the signal in the figure is a clock signal, there is a group of 8-bit data lines in parallel, powered by the same power supply of the same chip, and the current return path is the same. If the data line level is flipped in the same direction at the same time, a large reverse current will be induced on the clock. If the clock line is not well matched, this crosstalk is enough to have a fatal effect on the clock signal. The intensity of this crosstalk is not proportional to the absolute value of the high and low levels of the interference source, but is proportional to the current change rate of the interference source.

For a purely resistive load, the crosstalk current is proportional to dI/dt=dV/(T10%-90%*R).

In the formula, dI/dt (current change rate), dV (swing amplitude of the interference source) and R (interference source load) all refer to the parameters of the interference source (if it is a capacitive load, dI/dt is inversely proportional to the square of T10%-90%.).

It can be seen from the formula that the crosstalk of a low-speed signal is not necessarily smaller than that of a high-speed signal. In other words, what we said is: a 1kHZ signal is not necessarily a low-speed signal, and the edge situation should be considered comprehensively. For a signal with a very steep edge, it contains many harmonic components and has a large amplitude at each frequency multiplication point. Therefore, when selecting a device, you should also pay attention to it. Don’t blindly choose a chip with a fast switching speed. Not only is the cost high, but it will also increase crosstalk and EMC problems.

Any adjacent power layer or other plane, as long as there is a suitable capacitor at both ends of the signal to provide a low-reactance path to GND, then this plane can be used as the return plane of this signal. In normal applications, the IO power supply of the chip corresponding to the transmitter and receiver is often consistent, and there is generally a 0.01-0.1uF decoupling capacitor between each power supply and the ground, and these capacitors are just at both ends of the signal, so the return effect of the power plane is second only to the ground plane. If other power planes are used for return, there is often no low-resistance path to the ground at both ends of the signal.

In this way, the current induced in the adjacent plane will find the nearest capacitor to return to the ground.

If this “nearest capacitor” is far away from the beginning or end, this return flow will also have to go through a “long journey” to form a complete return path, and this path is also the return path of the adjacent signal. The same return path has the same effect as the common ground interference, which is equivalent to crosstalk between signals.

For some unavoidable cross-power splitting situations, a high-pass filter composed of a capacitor or RC series connection can be connected across the splitting place (such as a 10-ohm resistor and a 680p capacitor, the specific value depends on the type of signal, that is, to provide a high-frequency return path and isolate the low-frequency crosstalk between the planes). This may involve adding capacitors between power planes, which seems a bit funny, but it is definitely effective. If some specifications do not allow it, the two planes can be connected to the ground with capacitors at the split point.

For the case of using other planes for return current, it is best to add a few small capacitors to the ground at both ends of the signal to provide a return current path. However, this approach is often difficult to achieve. Because most of the surface space near the terminal is occupied by matching resistors and chip decoupling capacitors.