Design of EMC of hybrid integrated circuits
This paper elaborates on the causes of electromagnetic interference of hybrid integrated circuits, and proposes the issues that should be paid attention to and the specific measures to be taken in the electromagnetic compatibility design of the system in combination with the process characteristics of hybrid integrated circuits, laying the foundation for improving the electromagnetic compatibility of hybrid integrated circuits.
1 Introduction
Hybrid integrated circuits (Hybrid Integrated Circuit) are integrated circuits made by combining semiconductor integration technology with thick (thin) film technology. Hybrid integrated circuits are made by using film forming methods on substrates to make thick film or thin film components and their interconnections, and on the same substrate, discrete semiconductor chips, monolithic integrated circuits or micro components are mixed and assembled, and then packaged. It has the characteristics of high assembly density, high reliability, and good electrical performance.
With the reduction of circuit board size, increase of wiring density and continuous increase of operating frequency, the electromagnetic interference phenomenon in the circuit is becoming more and more prominent, and the electromagnetic compatibility problem has become the key to whether an electronic system can work normally. The electromagnetic compatibility design of circuit boards has become the key to system design.
2 Principles of electromagnetic compatibility
Electromagnetic compatibility refers to the ability of electronic equipment and power supplies to work normally and reliably under certain electromagnetic interference environments, and also the ability of electronic equipment and power supplies to limit their own electromagnetic interference and avoid interference with other electronic equipment around them.
The occurrence of any electromagnetic interference must meet three basic conditions:
first, there must be an interference source, that is, a device or equipment that generates harmful electromagnetic fields; second, there must be a way to propagate interference, which is generally believed to have two ways: conduction coupling and radiation coupling; third, there must be sensitive equipment that is susceptible to interference.
Therefore, solving electromagnetic compatibility problems should target the three elements of electromagnetic interference and solve them one by one:
reduce the interference intensity of the interference-generating components; cut off the propagation path of the interference; reduce the system’s sensitivity to interference.
The electromagnetic interference that exists in hybrid integrated circuit design includes: conducted interference, crosstalk interference, and radiated interference.
When solving EMI problems, first determine whether the coupling path of the emission source is conducted, radiated, or crosstalk. If a high-amplitude transient current or a rapidly rising voltage appears near a conductor carrying a signal, the problem of electromagnetic interference is mainly crosstalk. If there is a complete circuit connection between the interference source and the sensitive device, it is conducted interference. Radiated interference will occur between two parallel wires that transmit high-frequency signals.
3 Electromagnetic compatibility design
When designing the electromagnetic compatibility of hybrid integrated circuits, the first thing to do is to do functional testing. In the circuit where the scheme has been determined, check whether the electromagnetic compatibility indicators can meet the requirements. If not, modify the parameters to meet the indicators, such as transmission power, operating frequency, and reselect devices. The second is to do protective design, including filtering, shielding, grounding and overlap design. The third is to do layout adjustment design, including overall layout inspection, layout inspection of components and wires, etc. Usually, the electromagnetic compatibility design of the circuit includes: selection of processes and components, circuit layout and wiring layout, etc.
3.1 Selection of processes and components
There are three manufacturing processes for hybrid integrated circuits to choose from: single-layer thin film, multi-layer thick film and multi-layer co-fired thick film. The thin film process can produce small-size, low-power and high-current density components required for high-density hybrid circuits. It has the characteristics of high quality, stability, reliability and flexibility, and is suitable for high-speed, high-frequency and high-packaging density circuits. But only single-layer wiring can be done and the cost is relatively high.
The multi-layer thick film process can manufacture multi-layer interconnected circuits at a lower cost.
From the perspective of electromagnetic compatibility, multi-layer wiring can reduce the electromagnetic radiation of the circuit board and improve the anti-interference ability of the circuit board. Because a special power layer and ground layer can be set up, the distance between the signal and the ground line is only the distance between the layers. In this way, the loop area of all signals on the board can be minimized, thereby effectively reducing differential mode radiation.
Among them, the multi-layer co-fired thick film process has more advantages and is the mainstream technology for passive integration.
It can realize more layers of wiring, easy to embed components, improve assembly density, and has good high-frequency characteristics and high-speed transmission characteristics. In addition, it has good compatibility with thin film technology. The combination of the two can achieve a hybrid multi-layer circuit with higher assembly density and better performance.
The active devices in the hybrid circuit generally use bare chips.
When there are no bare chips, the corresponding packaged chips can be selected. In order to obtain the best EMC characteristics, surface-mount chips should be selected as much as possible. When selecting chips, try to use low-speed clocks on the premise of meeting the product technical indicators. Never use AC when HC can be used, and do not use HC if CMOS4000 can work. The capacitor should have a low equivalent series resistance to avoid large attenuation of the signal.
The package of the hybrid circuit can use a base and shell cover made of Kovar metal, parallel seam welding, which has a good shielding effect.
3.2 Circuit layout
When dividing the layout of the hybrid microcircuit, three main factors should be considered first: the number of input/output pins, device density and power consumption. A practical rule is that the area occupied by the sheet component is 20% of the substrate, and the power dissipation per square inch is not more than 2W.
In terms of device layout, in principle, related devices should be as close as possible, digital circuits, analog circuits and power circuits should be placed separately, and high-frequency circuits should be separated from low-frequency circuits. Devices that are prone to noise, small current circuits, large current circuits, etc. should be kept as far away from logic circuits as possible. The main interference and radiation sources such as clock circuits and high-frequency circuits should be arranged separately, away from sensitive circuits. The input and output chips should be located close to the I/O exit of the hybrid circuit package.
The high-frequency components should be connected as short as possible to reduce the distributed parameters and electromagnetic interference between each other.
The components that are susceptible to interference should not be too close to each other, and the input and output should be as far away as possible. The oscillator should be as close to the location of the clock chip as possible, and away from the signal interface and low-level signal chip.
The components should be parallel or perpendicular to one side of the substrate, and the components should be arranged in parallel as much as possible.
This will not only reduce the distributed parameters between the components, but also conform to the manufacturing process of the hybrid circuit and be easy to produce.
The lead-out pads of the power supply and ground on the hybrid circuit substrate should be arranged symmetrically, and it is best to evenly distribute many power supply and ground I/O connections. The mounting area of the bare chip is connected to the most negative potential plane.
When selecting a multi-layer hybrid circuit, the inter-layer arrangement of the circuit board changes with the specific circuit, but generally has the following characteristics.
(1) The wiring layer should be arranged as close to the power supply or ground plane as possible to produce a flux cancellation effect.
(2) The power supply and ground layer are allocated in the inner layer, which can be regarded as a shielding layer, which can well suppress the common-mode RF interference inherent in the circuit board and reduce the distributed impedance of the high-frequency power supply.
(3) The power plane and ground plane in the board should be as close to each other as possible. Generally, the ground plane is above the power plane. In this way, the interlayer capacitance can be used as a smoothing capacitor for the power supply. At the same time, the ground plane can shield the radiation current distributed on the power plane.
3.3 Wire layout
In circuit design, people often only focus on improving the wiring density or pursuing uniform layout, ignoring the impact of line layout on preventing interference, causing a large number of signals to radiate into space to form interference, which may cause more electromagnetic compatibility problems. Therefore, good wiring is the key to determining the success of the design.
3.3.1 Ground wire layout
The ground wire is not only the potential reference point for the circuit operation, but also a low-impedance loop for the signal. The most common interference on the ground wire is the ground loop interference caused by the ground loop current. Solving this type of interference problem is equivalent to solving most of the electromagnetic compatibility problems.
The noise on the ground wire mainly affects the ground level of the digital circuit, and when the digital circuit outputs a low level, it is more sensitive to the noise of the ground wire. The interference on the ground wire may not only cause malfunction of the circuit, but also cause conduction and radiation emissions. Therefore, the key to reducing these interferences is to reduce the impedance of the ground line as much as possible (for digital circuits, reducing the ground inductance is particularly important).
The layout of the ground line should pay attention to the following points:
(1)When multiple chips are installed on the board, there will be a large potential difference on the ground line. The ground line should be designed as a closed loop to improve the noise tolerance of the circuit.
(2) For circuit boards with both analog and digital functions, the analog ground and digital ground are usually separated and only connected at the power supply.
(3) According to different power supply voltages, ground lines are set separately for digital circuits and analog circuits.
(4) The common ground line should be as thick as possible. When using a multi-layer thick film process, a special ground line surface can be set, which helps to reduce the loop area, but also reduces the efficiency of the receiving antenna. It can also serve as a shield for the signal line.
(5) Comb-shaped ground lines should be avoided. This structure makes the signal return loop very large, which will increase radiation and sensitivity, and the common ground between chips is not good. Impedance may also cause circuit misoperation.
3.3.2 Layout of power lines
Generally speaking, in addition to interference caused directly by electromagnetic radiation, electromagnetic interference caused by power lines is the most common. Therefore, the layout of the power lines is also very important, and the following rules should usually be followed.
(1) Decoupling should be performed between the power pin and the ground pin of the chip. The decoupling capacitor uses a 0.01uF chip capacitor and should be installed close to the chip to minimize the loop area of the decoupling capacitor.
(2) When selecting a surface-mount chip, try to select a chip with a power pin and a ground pin that are close together, which can further reduce the power supply loop area of the decoupling capacitor and is conducive to achieving electromagnetic compatibility.
(3) The power line should be as close to the ground line as possible to reduce the power supply loop area, reduce differential mode radiation, and help reduce circuit crosstalk. Interference. The power supply loops of different power supplies should not overlap with each other.
(4) When using a multi-layer process, separate the analog power supply and the digital power supply to avoid mutual interference. Do not overlap the digital power supply with the analog power supply, otherwise coupling capacitance will be generated, destroying the separation.
(5) The power plane and the ground plane can be completely isolated by dielectric. When the frequency and speed are very high, a dielectric slurry with a low dielectric constant should be used. The power plane should be close to the ground plane and arranged under the ground plane to shield the radiation current distributed on the power plane.
3.3.3 Layout of signal lines
When using a single-layer thin film process, a simple and applicable method is to lay out the ground line first, then arrange the key signals, such as high-speed clock signals or sensitive circuits close to their ground loops, and finally lay out other circuits. It is best to arrange the layout according to the order of signal flow so that the signal flow on the circuit board is smooth.
If you want to minimize EMI, keep the signal line as close as possible to the return signal line it forms, so that the loop area is as small as possible to avoid radiation interference. Low-level signal channels cannot be close to high-level signal channels and unfiltered power lines, and noise-sensitive wiring should not be parallel to high-current and high-speed switching lines.
If possible, lay out all key traces in strip lines. Incompatible signal lines (digital and analog, high speed and low speed, high current and low current, high voltage and low voltage, etc.) should be kept away from each other and not run parallel. Crosstalk between signals is extremely sensitive to the length and spacing of adjacent parallel traces, so try to increase the spacing between high-speed signal lines and other parallel signal lines and reduce the parallel length.
The inductance of the conductive strip is proportional to its length and the logarithm of its length, and inversely proportional to the logarithm of its width.
Therefore, the conduction band should be as short as possible, and the length of each address line or data line of the same component should be kept consistent as much as possible. The wires used as circuit input and output should avoid being parallel to each other.
It is best to add a ground wire between them to effectively suppress crosstalk. The wiring density of low-speed signals can be relatively large, and the wiring density of high-speed signals should be as small as possible.
In the multi-layer thick film process, in addition to complying with the rules of single-layer wiring, it should also be noted that:
Try to design a separate ground plane, and arrange the signal layer adjacent to the ground layer. When it cannot be used, a ground wire must be set near the high-frequency or sensitive circuit. The signal lines distributed on different layers should be perpendicular to each other, so as to reduce the electric and magnetic field coupling interference between the lines; the signal lines on the same layer should maintain a certain distance, and it is best to isolate them with the corresponding ground wire loop to reduce the signal crosstalk between the lines.
Each high-speed signal line should be limited to the same layer. The signal line should not be too close to the edge of the substrate, otherwise it will cause characteristic impedance changes, and it is easy to generate fringe fields and increase outward radiation.
3.3.4 Layout of clock lines
Clock circuits occupy an important position in digital circuits and are also the main source of electromagnetic radiation. The spectrum of energy radiated by a clock signal with a 2ns rising edge can reach 160MHz. Therefore, designing a good clock circuit is the key to ensuring the electromagnetic compatibility of the entire circuit. Regarding the layout of the clock circuit, there are the following points of attention:
(1) All the conduction strips connected to the input/output of the crystal oscillator should be as short as possible to reduce noise interference and the influence of distributed capacitance on the crystal oscillator.
(2) The ground wire of the crystal oscillator capacitor should be connected to the device using a conduction strip that is as wide and short as possible; the digital ground pin closest to the crystal oscillator should have as few vias as possible.
(3) Do not use a daisy chain structure to transmit the clock signal, but a star structure, that is, all clock loads are directly connected to the clock power driver.
4 Conclusion
The innovation of the article: Starting from improving the electromagnetic compatibility of the system, combined with the process characteristics of hybrid integrated circuits, this article proposes the issues that should be paid attention to and the specific measures to be taken in the design of hybrid integrated circuits.
