Design of Lossless Image Compression System Based on FPGA
Digital signal processing technology has been successfully applied to signal filtering, speech, image, audio, information systems, control and instrumentation equipment. The introduction of programmable digital signal processors in the 1970s has made DSP technology advance by leaps and bounds and achieved great success. These PDSPs are based on the architecture of the reduced instruction set (RISC) computer paradigm. Its advantage comes from the fact that the multiplication-accumulation operation (MAC) of most signal processing algorithms is very intensive. Through the multi-stage pipeline architecture, the PDSP can obtain a MAC speed that is only limited by the speed of the array multiplier. From this, it can be considered that FPGA can also be used to implement MAC units and has a speed advantage. However, if the PDSP can meet the required MAC speed, then the PDSP has a cost advantage in terms of cost, but as the cost of FPGA decreases, this advantage is shrinking. On the other hand, we now also find many high-bandwidth signal processing applications, such as radio, multimedia or satellite communications, FPGA technology can provide more bandwidth through multi-stage MAC units on a chip. In addition, in algorithms such as CORDIC ($1087.5000), NTT and error correction algorithms, FPGA is more efficient than PDSP.
The key to FPGA technology is to use powerful design tools to:
▲ Shorten the development cycle.
▲ Improve the utilization of device resources.
▲ Provide synthesizer options, such as choosing between optimal speed and design scale.
FPGA has obvious characteristics such as serial and parallel working modes and high integration, high speed and high reliability. Its clock delay can reach nanoseconds. At the same time, in chip-based design, it can reduce the number of chips, reduce the system size, reduce energy consumption, and improve the performance indicators and reliability of the system.
It is precisely because of these advantages that FPGA has a very broad application prospect in ultra-high-speed application fields and real-time measurement and control. In the field of high-reliability applications, if the design is proper, there will be no problems such as unreliable reset of MCU and possible PC running away. The high reliability of FPGA is also reflected in the fact that almost the entire system can be downloaded to the same chip to realize the so-called system on chip, thereby greatly reducing the size.
Compared with AMU design, FPGA has the significant advantages of short development cycle, low investment risk, fast product launch, strong market adaptability and large room for hardware upgrade. Moreover, when the product is finalized and the output is expanded, the VHDL design that has been fully tested in production can be quickly put into ASIC production.
With the development of large-scale field programmable logic devices, system design has entered a new era of “system on programmable chip” (SOPC); chips are moving towards high density, low voltage and low power consumption: microprocessors, digital signal processors, memory, logic circuits and analog circuits can be integrated on a single chip on SOC chips. If the programmable logic circuit IP core is integrated into the SOC chip, the flexibility and effectiveness of the SOC chip will be greatly improved, and the design cycle of the SOC chip will be shortened. Therefore, major international companies are actively expanding their IP libraries to optimize resources to better meet user needs and expand the market.
In summary, compared with ASIC and general-purpose DSP, FPGA devices can be applied to the field of digital signal processing with the advantages of high speed, real-time, low cost and high flexibility. Using FPGA to realize digital signal processing has become a new trend in the field of digital signal processing. It can completely replace general-purpose DSP chips or work as a coprocessor of general-purpose DSP chips. If the general-purpose processor and FPGA are integrated together, the operations that require multiple clock cycles are handed over to FPGA to complete, and the DSP chip mainly completes the single-clock operation and controls the “reconfigurable calculation” function of FPGA, the advantages of both will be better brought into play.
FPGA implementation of butterfly operation unit
The butterfly operation unit is the basic unit of the FFT processor, which is used to calculate the FFT of two points. Since the butterfly operation unit is composed of a complex adder, a complex subtractor and a twiddle factor complex multiplier, the butterfly operation unit can be designed and implemented using the twiddle factor complex multiplier designed above and the lpm_add_sub module in MAX+PLUSII. The VHDL code of the radix-2 FFT butterfly operation unit is shown in Appendix B. As can be seen from the code, the butterfly processor is implemented by an adder, a subtractor, and a twiddle factor multiplier instantiated as a component. The input and output block diagram of the corresponding hardware implementation is shown in the figure below:
Input and output block diagram of butterfly processor
Simulation is performed when the input values are A=20+30J, B=50+45j, and the twiddle factor C+jS=256×e∧jpi/9=121+j39. The simulation waveform is shown in the figure below:
VHDL simulation waveform of butterfly operation unit
It can be seen that the output results of the designed butterfly processor when the input A=20+30J, B=50+45j, and the twiddle factor C+jS=256×e∧jpi/9=121+j39 are completely consistent with the results calculated theoretically, which shows the correctness of the butterfly processing unit designed based on VHDL language.
This paper discusses the application of FPGA in digital signal processing by designing an FPGA-based FFT. This paper focuses on the design and implementation of the butterfly operation unit, and conducts simulation. By comparison, it can be seen that the simulation results are in good agreement with the theoretical values. The biggest advantage of this system is that it utilizes the rich logic resources of FPGA devices, the embedded RAM, ROM blocks and their flexible programmable characteristics to greatly improve the operation speed compared with traditional methods. Of course, the price paid is that this parallel structure requires a lot of hardware resources.
With the continuous improvement of chip integration, the superiority of FFT operations implemented by this parallel structure will become more and more obvious. Moreover, the FFT implemented by this structure is easy to expand, and only the number of butterflies and the number of cycles need to be increased. The FFT/IFFT processor based on FPGA is much faster than the general DSP due to its hardware parallelism. FPGA has thousands of lookup tables and triggers, so the FPGA platform can achieve faster speeds than general DSPs at a lower cost. Using FPGA technology, high performance can also be achieved, cost requirements can be met, and the flexibility to optimize new designs quickly and effectively can be enjoyed. This FFT/IFFT processor based on parallel algorithms can be widely used in high-speed signal processing systems. And from the design of the FFT processor, it can be seen that the front-end programmable digital signal processing algorithms, such as FIR and IIR filters, can be built using FPGAs.
The use of FPGAs to implement digital signal processing will be widely used in modern communications. DSP IP is an ideal choice for emerging applications such as 3G wireless communications, digital audio and video image processing, broadcasting, multi-channel multipoint distribution services (MMDS), and orthogonal frequency division multiplexing (OFDM) systems. The flexibility of programmable logic and soft IP cores allows companies to quickly adapt their designs to new standards.
Currently, Altera has designed and implemented DSP functional blocks. Altera’s DSP IP suite includes standard DSP functions (such as Turbo ($2175.0000) decoders). IP cores are statically parameterized so that the MegaWizard Plug-In Manager generates the most efficient hardware based on a given set of parameters. These plug-ins allow designers to customize IP without changing the design source code. Moreover, soft IP can be immediately imported into new Altera FPGA device families. This solution meets the requirements of both design and production departments.
It can be seen that hardware and software designers can use programmable logic to develop various DSP application solutions. Programmable solutions can better adapt to rapidly changing standards, protocols and performance requirements. With the emergence of new FPGA systems, the increase in the number of DSP IP cores and tools, DSP applications using programmable logic continue to increase. FPGA devices can be applied to the field of digital signal processing with the advantages of high speed, real-time, low cost and high flexibility. It can completely replace general-purpose DSP chips or work as a coprocessor of general-purpose DSP chips.
