PCB-level electromagnetic compatibility design of DSP high-speed system
This paper starts from improving the electromagnetic compatibility of the system, combines the process characteristics of hybrid integrated circuits, and puts forward the issues that should be paid attention to and the specific measures to be taken in the design of hybrid integrated circuits. Hybrid integrated circuits (Hybrid Integrated Circuit) are integrated circuits made by combining semiconductor integration technology with thick (thin) film technology. Hybrid integrated circuits are made by using film forming methods on substrates to make thick film or thin film components and their interconnections, and on the same substrate, separate semiconductor chips, monolithic integrated circuits or micro components are mixed and assembled, and then packaged. It has the characteristics of high assembly density, high reliability, and good electrical performance.
Principle of electromagnetic compatibility
Electromagnetic compatibility refers to the ability of electronic equipment and power supplies to work normally and reliably under certain electromagnetic interference environments. It is also the ability of electronic equipment and power supplies to limit their own electromagnetic interference and avoid interfering with other electronic equipment around them.
The occurrence of any electromagnetic interference must meet three basic conditions: first, there must be an interference source, that is, a device or equipment that generates harmful electromagnetic fields; second, there must be a way to propagate interference, which is generally believed to have two ways: conduction coupling and radiation coupling; third, there must be sensitive equipment that is susceptible to interference.
Therefore, solving electromagnetic compatibility problems should target the three elements of electromagnetic interference and solve them one by one: reduce the interference intensity of the interference generating components; cut off the propagation path of the interference; reduce the sensitivity of the system to interference.
The electromagnetic interference existing in hybrid integrated circuit design includes: conducted interference, crosstalk interference and radiated interference.
When solving EMI problems, we should first determine whether the coupling path of the emission source is conducted, radiated or crosstalk. If a high-amplitude transient current or a rapidly rising voltage appears near a conductor carrying a signal, the electromagnetic interference problem is mainly crosstalk. If there is a complete circuit connection between the interference source and the sensitive device, it is conducted interference. And radiated interference will be generated between two parallel wires transmitting high-frequency signals.
Electromagnetic compatibility design
When designing electromagnetic compatibility of hybrid integrated circuits, we should first do functional testing, and check whether the electromagnetic compatibility indicators can meet the requirements in the circuit where the scheme has been determined. If not, we should modify the parameters to meet the indicators, such as transmission power, operating frequency, and reselecting devices. The second is to do protective design, including filtering, shielding, grounding and overlapping design. The third is to make an adjustable design for the layout, including the inspection of the overall layout, the layout inspection of components and wires, etc. Usually, the electromagnetic compatibility design of the circuit includes: the selection of processes and components, the layout of circuits and the layout of wires, etc. Selection of processes and components
There are three manufacturing processes for hybrid integrated circuits to choose from, single-layer thin film, multi-layer thick film and multi-layer co-fired thick film. The thin film process can produce small-size, low-power and high-current density components required for high-density hybrid circuits. It has the characteristics of high quality, stability, reliability and flexibility, and is suitable for high-speed, high-frequency and high-packaging density circuits. But only single-layer wiring can be done and the cost is relatively high.
The multi-layer thick film process can manufacture multi-layer interconnected circuits at a lower cost.
From the perspective of electromagnetic compatibility, multi-layer wiring can reduce the electromagnetic radiation of the circuit board and improve the anti-interference ability of the circuit board. Because a special power layer and ground layer can be set up, the distance between the signal and the ground wire is only the distance between the layers. In this way, the loop area of all signals on the board can be minimized, thereby effectively reducing differential mode radiation.
Among them, the multi-layer co-fired thick film process has more advantages and is the mainstream technology of passive integration at present. It can realize more layers of wiring, easy to embed components, improve assembly density, and have good high-frequency characteristics and high-speed transmission characteristics. In addition, it has good compatibility with thin film technology. The combination of the two can realize hybrid multilayer circuits with higher assembly density and better performance.
Active devices in hybrid circuits generally use bare chips.
When there are no bare chips, corresponding packaged chips can be selected. In order to obtain the best EMC characteristics, surface-mount chips should be selected as much as possible. When selecting chips, try to use low-speed clocks on the premise of meeting product technical indicators. Never use AC when HC can be used, and do not use HC if CMOS4000 can work. Capacitors should have low equivalent series resistance to avoid large attenuation of signals.
The packaging of hybrid circuits can use Kovar metal base and shell cover, parallel seam welding, which has a good shielding effect.
Circuit layout
When dividing the layout of hybrid microcircuits, three main factors should be considered first: the number of input/output pins, device density and power consumption. A practical rule is that the area occupied by sheet components is 20% of the substrate, and the power dissipation per square inch is not more than 2W.
In terms of device layout, in principle, related devices should be placed as close as possible, digital circuits, analog circuits and power circuits should be placed separately, and high-frequency circuits should be separated from low-frequency circuits. Devices that are prone to noise, small current circuits, large current circuits, etc. should be kept as far away from logic circuits as possible. Main interference and radiation sources such as clock circuits and high-frequency circuits should be arranged separately and away from sensitive circuits. Input and output chips should be located close to the I/O exit of the hybrid circuit package.
High-frequency components should be connected as short as possible to reduce distributed parameters and mutual electromagnetic interference. Components that are susceptible to interference should not be too close to each other, and input and output should be kept as far away as possible. The oscillator should be as close as possible to the location where the clock chip is used, and away from signal interfaces and low-level signal chips.
Components should be parallel or perpendicular to one side of the substrate, and components should be arranged in parallel as much as possible. This will not only reduce the distributed parameters between components, but also conform to the manufacturing process of the hybrid circuit and be easy to produce.
The lead-out pads for power and ground on the hybrid circuit substrate should be arranged symmetrically, and it is best to evenly distribute many power and ground I/O connections. The mounting area of the bare chip is connected to the most negative potential plane.
When selecting a multi-layer hybrid circuit, the interlayer arrangement of the circuit board changes with the specific circuit, but generally has the following characteristics.
(1) The wiring layer should be arranged as close to the power or ground plane as possible to produce a flux cancellation effect.
(2) The power and ground layers are distributed in the inner layer, which can be regarded as shielding layers, which can effectively suppress the common-mode RF interference inherent in the circuit board and reduce the distributed impedance of the high-frequency power supply.
(3) The power plane and ground plane in the board are as close to each other as possible. Generally, the ground plane is above the power plane. In this way, the interlayer capacitance can be used as the smoothing capacitance of the power supply. At the same time, the ground plane plays a shielding role for the radiation current distributed on the power plane.
Wire layout
In circuit design, people often only focus on improving the wiring density or pursuing uniform layout, ignoring the impact of line layout on preventing interference, causing a large number of signals to radiate into space to form interference, which may cause more electromagnetic compatibility problems. Therefore, good wiring is the key to determining the success of the design.
Ground wire layout
The ground wire is not only the potential reference point for the circuit operation, but also can be used as a low-impedance loop for the signal. The most common interference on the ground wire is the ground loop interference caused by the ground loop current. Solving this type of interference problem is equivalent to solving most of the electromagnetic compatibility problems.
The noise on the ground line mainly affects the ground level of the digital circuit, and when the digital circuit outputs a low level, it is more sensitive to the noise of the ground line. The interference on the ground line may not only cause the circuit to malfunction, but also cause conducted and radiated emissions. Therefore, the key to reducing these interferences is to reduce the impedance of the ground line as much as possible (for digital circuits, reducing the ground line inductance is particularly important).
The layout of the ground line should pay attention to the following points:
(1) When there are multiple chips on the board, there will be a large potential difference on the ground line. The ground line should be designed as a closed loop to improve the noise tolerance of the circuit.
(2) For circuit boards with both analog and digital functions, the analog ground and digital ground are usually separated and only connected at the power supply.
(3) According to different power supply voltages, ground lines are set separately for digital circuits and analog circuits.
(4) The common ground line should be as thick as possible. When using a multi-layer thick film process, a ground line surface can be specially set up, which helps to reduce the loop area and also reduces the efficiency of the receiving antenna. It can also be used as a shield for the signal line.
(5) Avoid comb-shaped ground wires. This structure makes the signal return loop very large, which will increase radiation and sensitivity, and the common impedance between chips may also cause circuit misoperation.
Power line layout
Generally speaking, in addition to interference caused directly by electromagnetic radiation, electromagnetic interference caused by power lines is the most common. Therefore, the layout of power lines is also very important, and the following rules should usually be followed.
(1) Decoupling should be performed between the power pin and the ground pin of the chip. The decoupling capacitor uses a 0.01uF chip capacitor and should be installed close to the chip to minimize the loop area of the decoupling capacitor.
(2) When using a surface-mount chip, try to use a chip with a power pin and a ground pin close to each other, which can further reduce the power supply loop area of the decoupling capacitor and help achieve electromagnetic compatibility.
(3) The power line should be as close to the ground line as possible to reduce the power supply loop area, reduce differential mode radiation, and help reduce circuit interference. The power supply loops of different power supplies should not overlap with each other.
(4) When using a multi-layer process, separate the analog power supply and the digital power supply to avoid mutual interference. Do not overlap the digital power supply and the analog power supply, otherwise coupling capacitance will be generated, destroying the separation.
(5) The power plane and the ground plane can be completely isolated by dielectrics. When the frequency and speed are very high, a dielectric slurry with a low dielectric constant should be used. The power plane should be close to the ground plane and arranged below the ground plane to shield the radiation current distributed on the power plane.
Layout of signal lines
When using a single-layer film process, a simple and applicable method is to lay out the ground line first, then place the key signals, such as high-speed clock signals or sensitive circuits close to their ground loops, and finally lay out other circuits. The layout of the signal line is best arranged according to the flow sequence of the signal to make the signal flow on the circuit board smooth.
If you want to minimize EMI, keep the signal line as close as possible to the return signal line it forms, and make the loop area as small as possible to avoid radiation interference. Low-level signal channels should not be close to high-level signal channels and unfiltered power lines, and noise-sensitive wiring should not be parallel to high-current, high-speed switching lines.
If possible, lay out all key traces as strip lines. Incompatible signal lines (digital and analog, high speed and low speed, high current and low current, high voltage and low voltage, etc.) should be kept away from each other and should not be routed in parallel. Crosstalk between signals is extremely sensitive to the length and spacing of adjacent parallel lines, so try to increase the spacing between high-speed signal lines and other parallel signal lines and reduce the parallel length.
The inductance of the conductor is proportional to its length and the logarithm of its length, and inversely proportional to the logarithm of its width. Therefore, the conductor should be as short as possible, and the address lines or data lines of the same component should be kept as consistent in length as possible. The wires used as circuit input and output should be avoided from being parallel to each other as much as possible. It is best to add a ground wire between them to effectively suppress crosstalk. The wiring density of low-speed signals can be relatively large, and the wiring density of high-speed signals should be as small as possible.
In multi-layer thick film technology, in addition to complying with the rules of single-layer wiring, it should also be noted that:
Try to design a separate ground plane, and arrange the signal layer adjacent to the ground layer. When it cannot be used, a ground wire must be set near the high-frequency or sensitive circuit. Signal lines distributed on different layers should be perpendicular to each other, so as to reduce the coupling interference of electric and magnetic fields between lines; signal lines on the same layer should maintain a certain distance, and it is best to use corresponding ground line loops to isolate and reduce signal crosstalk between lines.
Each high-speed signal line should be limited to the same layer. The signal line should not be too close to the edge of the substrate, otherwise it will cause characteristic impedance changes and easily generate edge fields, increasing outward radiation.
Layout of clock lines
Clock circuits play an important role in digital circuits and are also the main source of electromagnetic radiation. The spectrum of radiation energy of a clock signal with a 2ns rising edge can reach 160MHz. Therefore, designing a good clock circuit is the key to ensuring electromagnetic compatibility of the entire circuit. Regarding the layout of the clock circuit, there are the following precautions:
(1) All conduction strips connected to the input/output of the crystal oscillator should be as short as possible to reduce noise interference and the influence of distributed capacitance on the crystal oscillator.
(2) The ground line of the crystal oscillator capacitor should be connected to the device using a wide and short conduction strip; the digital ground pin closest to the crystal oscillator should have as few vias as possible.
(3) Do not use a daisy chain structure to transmit clock signals. Instead, use a star structure, where all clock loads are directly connected to the clock power driver.
