Summary of Common Problems in PCB Design Signal Integrity

Increasingly high-frequency signal designs are closely linked to the steadily increasing performance of electronic systems. As system performance increases, PCB designers face increasing challenges: smaller die, denser board layouts, and lower power chip requirements. Technological advances are always accompanied by a series of problems. As system performance increases and high-speed design is adopted, some problems must be dealt with in the design environment.

Below, we summarize the challenges: Signal Quality IC manufacturers tend to lower core voltages and higher operating frequencies, which leads to a sharp increase in edge rates. Edge rates in unterminated designs will cause reflections and signal quality problems. Crosstalk

In high-speed signal design, dense paths often lead to crosstalk-the electromagnetic coupling phenomenon between traces on the PCB. Crosstalk can be edge coupling of traces on the same layer or broadside coupling on adjacent layers. Coupling is three-dimensional. Parallel paths and broadside traces cause more crosstalk than side-by-side trace paths.
Broadside-Coupled (top) vs. Edge-Coupled (bottom) Radiation

The fast edge rates in traditional designs can cause ringing on unterminated transmission lines, even when using the same frequency and trace length as before.

This results in substantially higher emissions, far exceeding the FCC/CISPR Class B limits for unterminated transmission lines.

at 10 nanoseconds (left) and 1 nanosecond (right) edge ratesDesign SolutionsSignal and power integrity issues can be intermittent and difficult to identify. So it’s best to find the root cause and eliminate it during the design process, rather than trying to fix it at a late stage and delaying production. With stackup planning tools, it’s easier to implement solutions to signal integrity issues in your design. Board Stackup Planning

The first priority for high-speed designs must be the board stackup. The substrate is the most important component of the assembly, and its specifications must be carefully planned to avoid impedance discontinuities, signal coupling, and excessive electromagnetic radiation. Keep the following tips and suggestions in mind when reviewing the board stackup for your next design:- All signal layers should be adjacent and tightly coupled to an uninterrupted reference plane that creates a well-defined return path to eliminate broadside crosstalk. Substrate for each signal layer is adjacent to the reference plane

• Good plane capacitance to reduce AC impedance at high frequencies. Tightly coupled inner electrical planes to reduce AC impedance on the top layer, greatly reducing electromagnetic radiation.
• Reducing dielectric height will greatly reduce crosstalk without affecting the available space on the board. – Substrate should be able to accommodate a range of different technologies. For example: 50/100 ohm digital, 40/80 ohm DDR4, 90 ohm USB.

Routing and Workflow

After carefully planning the stackup, the next step is to focus on routing the board. Based on the careful configuration of design rules and work areas, you can route the board most efficiently and successfully. The following tips can help you route more easily and avoid unnecessary crosstalk, radiation and signal quality issues:

• Simplify the view to clearly see the split planes and current loops. To do this, first determine which copper plane (ground or power) is the reference plane for each signal layer, and then turn on the signal layer and inner electrical plane to view them simultaneously. This will help you see the traces of the split planes more easily. image.pngMultiple signal layers (left), top layer, and adjacent plane views (right) – If a digital signal must cross a power reference plane, you can place one or two decoupling capacitors (100nF) close to the signal. This provides a current return path between the two supplies. – Avoid parallel routing and wide-edge routing, which can cause more crosstalk than side-by-side routing. – Unless you are using synchronous buses, keep parallel intervals as short as possible to reduce crosstalk. Space signal groups so that their address and data intervals are three times the trace width. – Be careful when using combined microstrip layers on the top and bottom layers of the board. This can cause crosstalk between traces on adjacent board layers, compromising signal integrity. – Route the clock (or strobe) signal with the longest delay per signal group, which ensures that data is established before the clock is read. – Route embedded signals between planes to help minimize emissions and provide ESD protection.