What should be checked when designing PCB

This article summarizes 148 inspection items that should be paid attention to when designing PCB, and I hope it will be helpful for your study.

A.Data input stage

1. Whether the data received in the process is complete (including: schematic diagram, *.brd file, bill of materials, PCB design instructions, PCB design or change requirements, standardization requirements, process design instructions)
2. Confirm that the PCB template is the latest
3. Confirm that the positioning device position of the template is correct
4. Whether the PCB design instructions, PCB design or change requirements, and standardization requirements are clear
5. Confirm that the prohibited placement of devices and wiring areas on the outline drawing have been reflected on the PCB template
6. Compare the outline drawing to confirm that the dimensions and tolerances marked on the PCB are correct, and the metallized holes and non-metallized holes are accurately defined
7. After confirming that the PCB template is correct, it is best to lock the structure file to avoid being moved due to erroneous operation

B.Post-layout inspection stage

8. Confirm whether all device packages are consistent with the company’s unified library and whether the package library has been updated (use viewlog to check the running results). If not, be sure to Update Symbols
9. Motherboard and daughterboard, single board and backplane, confirm that the signal and position correspond, the connector direction and silk screen marking are correct, and the daughterboard has anti-misinsertion measures, and the devices on the daughterboard and motherboard should not interfere
10. Are the components 100% placed?
11. Open the place-bound of the device TOP and BOTTOM layers to check whether the DRC caused by overlap is allowed
12. Are the mark points sufficient and necessary?
13. Heavier components should be placed near the PCB support points or support edges to reduce PCB warping
14. After the layout of the structural-related devices is completed, it is best to lock them to prevent misoperation and movement
15. Within 5mm around the crimping socket, no components with a height exceeding the crimping socket height are allowed on the front, and no components or solder joints are allowed on the back
16. Confirm whether the device layout meets the process requirements (focus on BGA, PLCC, and SMD sockets)
17. For components with metal shells, pay special attention not to collide with other components and leave enough space
18. Interface-related devices should be placed as close to the interface as possible, and the backplane bus driver should be placed as close to the backplane connector as possible
19. Whether the CHIP device on the wave soldering surface has been converted into a wave soldering package,
20. Whether there are more than 50 manual solder joints
21. When inserting components with higher axial height on the PCB, horizontal installation should be considered. Leave space for horizontal placement. And consider the fixing method, such as the fixed pad of the crystal oscillator
22. For devices that require heat sinks, confirm that there is enough spacing with other devices, and pay attention to the height of the main devices within the heat sink range

C. Functional inspection

23. Whether the digital circuit and analog circuit devices of the mixed analog board have been separated during layout, and whether the signal flow is reasonable
24. The A/D converter is placed across the analog-to-digital partition.
25. Is the layout of clock devices reasonable?
26. Is the layout of high-speed signal devices reasonable?
27. Are the termination devices placed reasonably (the source end matching series resistance should be placed at the driving end of the signal; the middle matching series resistance should be placed in the middle position; the terminal matching series resistance should be placed at the receiving end of the signal)
28. Are the number and position of decoupling capacitors of IC devices reasonable?
29. The signal line uses planes of different levels as reference planes. When crossing the plane division area, are the connection capacitors between the reference planes close to the signal routing area?
30. Is the layout of the protection circuit reasonable and conducive to division?
31. Is the fuse of the single-board power supply placed near the connector, and is there no circuit component in front?
32. Confirm that the strong signal and weak signal (power difference 30dB) circuits are laid out separately?
33. Are the devices that may affect the EMC experiment placed according to the design guidelines or reference successful experience? For example: the reset circuit of the panel should be slightly closer to the reset button

D.Heat generation

34. Keep heat-sensitive components (including liquid dielectric capacitors and crystal oscillators) as far away from high-power components, heat sinks and other heat sources as possible
35. Whether the layout meets the thermal design requirements and the heat dissipation channel (performed according to the process design documents)

E.Power supply

36. Is the IC power supply too far from the IC
37. Is the layout of the LDO and surrounding circuits reasonable
38. Is the layout of the surrounding circuits such as the module power supply reasonable
39. Is the overall layout of the power supply reasonable

F.Rule setting

40. Have all simulation constraints been correctly added to the Constraint Manager
41. Have the physical and electrical rules been set correctly (pay attention to the constraint settings of the power network and the ground network)
42. Is the spacing setting of the Test Via and Test Pin sufficient
43. Does the thickness and scheme of the stack meet the design and processing requirements
44. Have all differential line impedances with characteristic impedance requirements been calculated and controlled by rules?

F.Digital and analog

45. Have the routing of digital circuits and analog circuits been separated, and is the signal flow reasonable?
46. If the A/D, D/A and similar circuits have split ground, do the signal lines between the circuits run from the bridge point between the two grounds (except for differential lines)?
47. Signal lines that must cross the gap between the split power supplies should refer to the complete ground plane.
48. If the ground layer design is divided and not divided, ensure that the digital signal and analog signal are divided and routed.

G. Clock and high-speed part

49. Are the impedances of high-speed signal lines consistent in each layer?
50. Are high-speed differential signal lines and similar signal lines routed in equal length, symmetrical, and parallel to each other?
51. Make sure that the clock line is routed in the inner layer as much as possible
52. Make sure that the clock line, high-speed line, reset line and other strong radiation or sensitive lines have been routed as much as possible according to the 3W principle
53. Are there no bifurcated test points on the clock, interrupt, reset signal, 100M/1000M Ethernet, and high-speed signal?
54. Do low-level signals such as LVDS and TTL/CMOS signals meet 10

H as much as possible (H is the height of the signal line from the reference plane)?

55. Do the clock line and high-speed signal line avoid crossing the dense through-hole area or the device pins?
56. Does the clock line meet the (SI constraint) requirements (whether the clock signal routing is done with fewer vias, short routing, continuous reference plane, and the main reference plane is GND as much as possible; if the GND main reference plane is changed when changing layers, there is a GND via within 200mil from the via) If the main reference plane of different levels is changed when changing layers, is there a decoupling capacitor within 200mil from the via)?
57. Do the differential pairs, high-speed signal lines, and various BUS meet the (SI constraint) requirements?

I.EMC and reliability

58. For the crystal oscillator, is a ground layer laid under it? Is the signal line avoided from crossing between device pins? For high-speed sensitive devices, is the signal line avoided from crossing between device pins?
59. There should be no sharp angles or right angles on the signal routing of a single board (generally, continuous turns at an angle of 135 degrees are made, and it is best to use arc-shaped or calculated angle-cut copper foil for RF signal lines)
60. For double-sided boards, check whether the high-speed signal lines are routed close to their return ground lines; for multi-layer boards, check whether the high-speed signal lines are routed as close to the ground plane as possible
61. For signal routing on two adjacent layers, try to route them vertically
62. Avoid signal lines passing under power modules, common-mode inductors, transformers, and filters
63. Try to avoid long-distance parallel routing of high-speed signals on the same layer
64. Are there shielded vias on the edges of the board and the dividing edges of the digital ground, analog ground, and protection ground? Are multiple ground planes connected by vias? Is the via distance less than 1/20 of the wavelength of the highest frequency signal?
65. Is the signal routing corresponding to the surge suppression device short and thick on the surface?
66. Confirm that there are no islands, oversized slots, long ground plane cracks caused by oversized through-hole isolation plates or dense vias, and no thin strips and narrow channels in the power supply and ground layer.
67. Have ground vias been placed in places where signal lines cross layers more frequently (at least two ground planes are required)?

J. Power and ground

68. If the power/ground planes are split, try to avoid high-speed signal crossing on the split reference planes.
69. Confirm that the power supply and ground can carry enough current. Whether the number of vias meets the carrying requirements (estimation method: 1A/mm line width when the outer layer copper thickness is 1oz, 0.5A/mm line width for the inner layer, and double the short line current)
70. For power supplies with special requirements, whether the voltage drop requirements are met?
71. In order to reduce the edge radiation effect of the plane, the 20H principle should be met as much as possible between the power layer and the ground layer. (If conditions permit, the more the power layer is indented, the better).
72. If there is ground segmentation, does the segmented ground not form a loop?
73. Do the power planes of different adjacent layers avoid overlapping placement?
74. Is the isolation between the protection ground, -48V ground and GND greater than 2mm?
75. Is the -48V ground only the -48V signal return, and is it not connected to other grounds? If this is not possible, please explain the reason in the remarks column.
76. Is a 10~20mm protection ground laid near the connector panel, and is the layer connected with double rows of staggered holes?
77. Does the distance between the power line and other signal lines meet the safety requirements?

K. Prohibited areas

78. There should be no traces, copper foils and vias that may cause short circuits under metal shell devices and heat dissipation devices
79. There should be no traces, copper foils and vias that may cause short circuits around mounting screws or washers
80. Are there traces in the reserved position in the design requirements?
81. The distance between the inner layer of the non-metallized hole and the trace and copper foil should be greater than 0.5mm (20mil), and the outer layer should be 0.3mm (12mil). The distance between the inner layer of the single board puller wrench and the trace and copper foil should be greater than 2mm (80mil)
82. The distance between the copper foil and the wire to the board edge is recommended to be greater than 2mm and the minimum is 0.5mm
83. The distance between the inner layer copper foil and the board edge is 1 ~ 2 mm, and the minimum is 0.5mm

L. Pad outlet

84. For CHIP components (0805 and below packages) mounted on two pads, such as resistors and capacitors, the traces connected to their pads should preferably be symmetrically led out from the center of the pads, and the traces connected to the pads must have the same width. This rule can be ignored for traces with a width less than 0.3mm (12mil)
85. For pads connected to wider traces, is it best to have a narrow trace transition in the middle? (0805 and below packages)

86, The circuit should be led out from both ends of the pads of devices such as SOIC, PLCC, QFP, SOT, etc. as much as possible

M. Silkscreen

87, Whether the device number is missing, whether the position can correctly identify the device

88, Whether the device number meets the company’s standard requirements

89, Confirm the correctness of the device’s pin arrangement order, the first pin mark, the device’s polarity mark, and the connector’s direction mark

90, Whether the motherboard and the daughterboard’s plug-in direction mark correspond

91, Whether the backplane correctly marks the slot name, slot number, port name, and sheath direction

92, Confirm whether the silkscreen addition required by the design is correct

93, Confirm that the anti-static and RF board marks have been placed (for RF board)

N. Coding/barcode

94, Confirm that the PCB code is correct and meets the company’s specifications

95, Confirm that the PCB code position and layer of the single board are correct (should be in the upper left of the A side, silkscreen layer)

96, Confirm that the PCB coding position and layer of the backplane are correct (should be in the upper right corner of B, outer copper foil surface)

97, Confirm that there is a barcode laser printed white silk screen marking area

98, Confirm that there are no connecting lines and vias larger than 0.5mm below the barcode frame

99, Confirm that there are no components with a height exceeding 25mm within 20mm outside the barcode white silk screen area

O. Via

100, On the reflow soldering surface, vias cannot be designed on the pad. (The spacing between the normally opened via and the pad should be greater than 0.5mm (20mil), and the spacing between the green oil-covered via and the pad should be greater than 0.1 mm (4mil). Method: Open Same Net DRC, check DRC, and then close Same Net DRC)

101. The arrangement of vias should not be too dense to avoid causing large-scale breaks in the power and ground planes
102. The diameter of the drilled via should not be less than 1/10 of the board thickness

P. Process

103. Whether the device placement rate is 100%, whether the routing rate is 100% (if it does not reach 100%, it needs to be explained in the remarks)
104. Whether the dangling line has been adjusted to the minimum, and the retained dangling lines have been confirmed one by one;
105. Whether the process problems reported by the process department have been carefully checked

Q. Large area copper foil

106. For large copper foils on the top and bottom, if there is no special need, grid copper should be used [oblique grid for single board, orthogonal grid for backplane, line width 0.3mm (12 mil), spacing 0.5mm (20mil)]

107, Component pads in large copper foil areas should be designed as flower pads to avoid false soldering; when there is a current requirement, first consider widening the ribs of the flower pads, and then consider full connection

108, When laying copper over a large area, dead copper (islands) without network connection should be avoided as much as possible

109, For large copper foils, it is also necessary to pay attention to whether there are illegal connections and unreported DRCs

R. Test points

110, Are there enough test points for various power supplies and grounds (at least one test point for every 2A current)

111, Confirm that the networks without test points are confirmed to be streamlined

112, Confirm that no test points are set on plug-ins that are not installed during production

113, Test Via, Test Is the pin fixed (applicable to the board modification with unchanged test needle bed)

S.DRC

114, the Spacing Rule of Test via and Test pin should be set to the recommended distance first, check DRC, if DRC still exists, check DRC with the minimum distance setting

115, open the constraint setting to open, update DRC, and check whether there are any unallowed errors in DRC

116, confirm that DRC has been adjusted to the minimum, and confirm one by one for those DRCs that cannot be eliminated;

T.Optical positioning point

117, confirm that the PCB surface with mounted components has optical positioning symbols

118, confirm that the optical positioning symbols are not pressed (silk screen and copper foil routing)

119, optical The background of the optical positioning points should be the same, and confirm that the center of the optical point used in the whole board is ≥5mm from the edge

120, Confirm that the optical positioning reference symbol of the whole board has been assigned a coordinate value (it is recommended to place the optical positioning reference symbol in the form of a device), and it is an integer value in millimeters.

121, ICs with a pin center distance <0.5mm and BGA devices with a center distance less than 0.8 mm (31 mil) should set optical positioning points near the diagonal of the component

U. Solder mask inspection

122, Confirm whether there are special types of pads that have been properly opened (pay special attention to the hardware design requirements)

123, Whether the vias under the BGA are processed into oil-covered plug holes

124, Whether small windows or oil-covered plug holes have been made for vias other than test vias

125, Whether the opening of the optical positioning point avoids copper and wire exposure

126, Whether there are copper skins and correct openings for devices such as power chips and crystal oscillators that require copper skin for heat dissipation or grounding shielding. Components fixed by solder should have green oil to prevent large-area diffusion of solder

V. Drilling diagram

127. Are the PCB thickness, number of layers, silk screen color, warpage, and other technical specifications of Notes correct?
128. Are the layer names, stacking order, dielectric thickness, and copper foil thickness of the stacking diagram correct? Is impedance control required? Is the description accurate? Is the layer name of the stacking diagram consistent with its photolithography file name?

129, Turn off the Repeat code in the setting table, and the drilling accuracy should be set to 2-5

130, Are the hole table and drilling file up to date (must be regenerated when changing the hole)

131, Are there any abnormal hole diameters in the hole table, are the hole diameters of the crimping parts correct; are the hole diameter tolerances correctly marked?

132, Are the vias for the plug holes listed separately and marked with “filled vias”?

W. Photolithography

133, The photolithography file output should be in RS274X format as much as possible, and the accuracy should be set to 5:5

134, Is art_aper.txt up to date (274X is not required)

135, Are there any abnormal reports in the log file of the output photolithography file?

136, Confirm the edge and island of the negative layer

137, Use the photolithography inspection tool to check whether the photolithography file is consistent with the PCB Match (use comparison tools to compare when changing the board)

S Files Complete Set

138, PCB File: Product Model_Specification_Single Board Code_Version Number.brd

139, Backplane Liner Design File: Product Model_Specification_Single Board Code_Version Number-CB[-T/B].brd

140, PCB Processing File: PCB Coding.zip (including the photo-drawing files, aperture table, drilling files and ncdrill.log of each layer; the panel also needs the panel file *.dxf provided by the process), the backplane also needs to attach the lining file: PCB Coding-CB[-T/B].zip (including drill.ar

t, *.drl, ncdrill.log)

141, Process Design File: Product Model_Specification_Single Board Code_Version Number-GY.doc

142, SMT Coordinate File: Product Model_Specification_Single Board Code_Version Number-SMT.txt, (When outputting the coordinate file, confirm that Body center, Symbol origin can only be selected when it is confirmed that the origin of all SMD device libraries is the device center)

143, PCB board structure file: product model_specification_board code_version number-MCAD.zip (including .DXF and .EMN files provided by the structural engineer)

144, test file: product model_specification_board code_version number-TEST.ZIP (including testprep.log and untest.lst or *.drl test point coordinate files)

145, archive drawing file: product model specification-board name-version number.pdf, (including: cover, home page, silk screen of each layer, circuit of each layer, drilling diagram, backplane with lining board diagram)

Y.Standardization

146, Confirm that the cover and home page information are correct

147, Confirm that the drawing serial number (corresponding to the order of each layer of PCB) is correct

148, Confirm that the PCB code on the drawing frame is correct