FPGAs as Custom Peripherals for Embedded Processors

A digital peripheral can be defined as a piece of circuitry that converts a signal from an external (relative to the processor) pulse source into a form that can be accessed by the processor. This external pulse source may be as simple as a mechanical switch or as complex as a high-speed data link running an advanced communication protocol.

Regardless of the form of the external signal, the data must be provided in a form that the processor can accept.

This can be achieved through a simple system address/data bus interface or through some higher speed (or dedicated) data link depending on the required data bandwidth of the target system.

Field Programmable Gate Arrays (FPGAs) have a large amount of logic circuits, memory, and routing resources and have been used for ASIC prototyping and high-end system development. Such devices include up to 80,000 logic elements and multiple Mbits of on-chip RAM. These devices typically contain complex functions composed of commercially available intellectual property (IP) cores and user-customized logic devices to implement high-speed data paths and data processing functions.

In simpler systems, FPGAs are often used as a tool to perform simpler logic functions such as connection logic and system control functions to help integrate other functions on the board.

These devices have fewer logic and memory resources and lower overall performance. However, for some target applications, they can offer a cost advantage over high-performance devices and provide adequate performance. Today, it is not difficult to find an embedded processor that includes all the peripherals you need for your system. So, is there a need for custom peripherals or interfaces? The processor may not be the architecture you choose, may not work at the performance you require, and in many cases there are features that cannot be implemented on-chip in a typical embedded processor. If an external peripheral is used, it may not be compatible with the processor using older technology that is required to write legacy software.

One problem with having multiple variants of a processor is that each variant requires its own unique mask set and test program development. However, mask sets are becoming more expensive to manufacture, which will lead to fewer processor variants as embedded processor manufacturers try to narrow their product portfolios to reduce costs.

High-end and low-cost FPGAs have unique combinations of features that are targeted to a specific type of device and for a specific purpose.

Of course, because FPGAs are programmable and offer tremendous flexibility, there is no “just one” end market for any particular system. Small systems may require a high-end FPGA, while high-performance systems may require a lower-cost device. High-end devices such as the Altera Stratix family combine logic devices with large amounts of on-chip SRAM, dedicated digital signal processor (DSP) blocks, numerous high-bandwidth I/O standards, and onboard clock generation circuitry using phase-locked loops (PLLs). On-chip SRAM is particularly useful in buffering data from a complex peripheral to an external interface, so that data can be transferred from the FPGA to the processor asynchronously with data being received from an external source. Ensuring bandwidth requirements is most important when using high-speed peripherals, especially those running communications protocols.

Stratix digital signal processing devices integrate multipliers and adders to aid in the execution of signal processing algorithms.

Using these components in an FPGA offloads complex functions from the processor, which would be less efficient and could degrade final system performance. This use of coprocessors also enables the use of SRAM by using shared data memory to pass data between asynchronously running processors and signal processing functions.

Stratix FPGAs offer a wide range of high-performance I/O standards that can transfer data at very high data rates between the FPGA and data sources or between the FPGA and an embedded processor that supports a compatible interface standard. Several processors offer onboard Hypertransport and/or RapidIO interfaces that can transfer data using a matching IP core in the peripheral FPGA, both of which are available as a fully parameterized IP core from Altera or one of its AMPP partner companies. This is a viable method for achieving high-speed data transfer between an embedded processor and a peripheral FPGA.

The use of phase-locked loops enables FPGAs to operate with different internal clocks, so the processor interface and peripherals implemented in the FPGA can run at different speeds, and similarly, shared SRAM can be used to achieve rate matching and synchronization between clock domains. For systems requiring lower costs, a device from Altera’s Cyclone family offers a moderate amount of logic resources and memory, PLLs, and a reduced set of I/O standards. This type of device family is designed to be low-cost across the board, sacrificing some high-end features for this purpose. The lower density of the low-cost devices makes them more suitable for implementing peripherals that use the system address bus method to connect to the processor, or those that may use low-bandwidth peripherals such as SPI or I2C, which are used by most embedded processors as on-chip peripherals.

Finally, there are some specialized devices for FPGAs, such as those with built-in high-speed transceivers suitable for operation at frequencies up to 3.125GHz.

These devices can provide very high data bandwidth and are mainly used for complex communication systems within the FPGA structure. Such devices will support the higher data rates of RapidIO and/or Hypertransport interfaces within the system. The embedded processor is likely to be in the data path of this high-bandwidth data flow, but it wants to connect using a lower performance FPGA/processor standard, in which case the FPGA is responsible for performing monitoring functions of the input data for statistical information collection or fault monitoring.

High-level design tools such as SOPCBuilder (part of Altera QuartusII design software) facilitate easy integration of IP cores with custom logic devices. This connects the hardware-implemented peripheral (FPGA) directly to the embedded processor in the system through a simple (system address bus), complex (IP core-based bus such as PCI), or proprietary interface.

From a system design perspective, one of the main goals of using a standard interface is to make the peripheral transparent to the system software. If the system bus approach is used, the FPGA will be treated as any other memory-switching peripheral, unaffected by the contents of the FPGA. In fact, the peripherals inside the FPGA can even be completely redesigned without any changes to the system software. Even where a bus such as PCI is used as the interface (an embedded processor has a built-in PCI bridge), the programming model for the processor is no different than the traditional use of the PCI bus. FPGAs can also essentially pre-verify the system design.

As embedded processors continue to evolve, discrete peripherals do not necessarily follow the same interface or standard development trends. With the approach of implementing peripherals in FPGAs, the peripherals can be easily migrated to newer architectures (usually with minimal design effort), allowing the peripheral performance to keep up with the embedded processor. Peripheral devices can also be precisely customized to the needs of the user without compromise.

As can be seen above, although FPGAs are often used as system-level functional components (at the high end) and connecting logic circuits (at the low end), more value can be obtained by using them as companion chips to embedded processors. FPGAs can provide a variety of solutions to meet various performance/price requirements, and with on-board memory, common I/O standards, and clock circuits, they can also provide advantages that discrete, “off-the-shelf” peripheral devices do not have in many occasions. With high-end (Stratix), low-cost (Cyclone) and transceiver-based device (Stratix GX) series, Altera has a complete device product library to meet the expansion needs of various peripheral devices. In addition, Altera alone can provide more than 50 IP cores, and with advanced system design tools such as SOPCBuilder, FPGAs will play an increasingly important role in the implementation of peripheral devices in embedded memory-based systems.