Avoid mixed-signal system design pitfalls

Content: To successfully use today’s SOCs, board-level and system-level designers must understand how to best place components, route traces, and utilize protective components.

They are called digital cellular phones, but they contain more analog functions than the previous varieties of so-called analog cellular phones. In fact, any system that needs to process continuous state values ​​(such as speech, video, temperature, pressure, etc.) will have its analog capabilities, even if the word digital appears in its name. Today’s multimedia PCs are no exception. With voice and video input and output, urgent temperature monitoring of hot central processing units, and high-performance modems, these systems likewise have items on their mixed-signal feature list. There are more and more.

The trend of two systems creates new challenges for those doing hybrid designs. Portable communications and computing devices continue to shrink in size and weight while increasing functionality. Desktop systems continue to improve central processing unit capabilities and communication peripheral speeds. It is certainly difficult to design modern digital circuit boards while avoiding problems such as ringing, noise-induced errors, and ground potential jumps. But when you add analog signal lines that are susceptible to noise and approach digital data lines with square wave excitation, the problem becomes even more serious.

At the chip level, current SOCs (systems on chips) require expertise in logic circuits, analog circuits, and thermal dynamics design. To successfully use these ICs, board- and system-level designers need to understand how to best place components, route traces, and utilize protective components.

This article describes common pitfalls in today’s mixed-signal system design and provides some guidelines for clearing or moving away from them. However, before exploring specific issues and making recommendations, it is helpful to take a detailed look at how two trends in system design—miniaturization and speed—affect these issues.

1.The trend of “miniaturization”

Comparing cellular phones in 1999 with products from five years ago, the number of chips was much smaller, the weight and volume were significantly reduced, and the battery life was greatly extended. In this process, the main factor is the great progress in mixed-signal IC solutions. However, as chip geometries shrink and the spacing of wiring on circuit boards approaches, the laws of physics begin to emerge.
Parallel traces are getting closer and closer, producing more and more parasitic capacitive coupling, and this is simply the result of an inverse relationship with the square of the distance. In the past, there was only a few traces of space, but now there are many traces. As a result, Even capacitive coupling between non-adjacent traces can pose a problem.
Cellular phones, by their very nature, are devices that are held and used by humans.

On a cold day, you’re walking up and down the carpet, and you pick up your cell phone, and boom – that sends a high voltage, electrostatic discharge (ESD) pulse to the device. Without proper ESD protection, it is possible for one or more ICs to become damaged. However, adding external components to protect against ESD damage goes against the trend of miniaturization.

Another issue is energy management. Cell phone users want their batteries to last as long as possible between charges. This means that the DC-to-DC converter must be very efficient. Switching technology is the answer, but in this case the converter becomes its own potential source of noise. So converters must be carefully selected and placed, as well as interconnected. Also, since volume is a factor that cannot be ignored, components should be chosen that allow the use of passive components with the smallest physical size. If you use a linear voltage regulator, you should choose an ultra-low dropout type that can maintain the output at the minimum battery voltage. This allows the battery to discharge as much as possible before it no longer provides enough power.

2.“High-speed” trend

Comparing the specs of a mid-range PC in 1999 to those of five years earlier, its central processing unit was about an order of magnitude faster and the current drawn by the CPU was about an order of magnitude higher. When you combine high speed with high current, the “di/dt” part of the V=L(di/dt) relationship increases dramatically. In fact, a half-inch-long ground trace in a circuit board may induce voltages in excess of 1 volt on it. For converters, voltages induced on the ground reference line may cause operation to stop.
To achieve these higher speeds, ICs are designed and manufactured with deep sub-micron dimensions (e.g. 0.35μm). While this reduces the geometry and results in much faster performance, it also makes these devices more susceptible to latch-up and damage caused by transients. Moreover, these devices also require tighter energy management to comply with increasingly stringent allowable voltage ranges.

The current 10/100Ethernet network interface card (NIC) is a good example. The original 10Base-T chip is a large-size CMOS device and is relatively less sensitive to overvoltage damage. However, newer chips using 0.35μm linewidths are very sensitive to latch-up and failure due to transients – transients caused by electrical energy and lightning.
Modern servers, with SMP (symmetric multi-processing capability) architectures and CPUs operating at 500MHz or above, are good examples of energy distribution challenges. You can’t simply build a 5V supply and run the wiring to the corresponding bus. Current switching up to 20A or 30A at 500MHz, which requires virtually a separate converter at each point-of-use, plus a larger primary voltage source for all of these converters Provide power.

The trend requires hotswap capabilities, which means you need to be able to insert and remove circuit boards into the existing system. Doing so also predicts the occurrence of transients. As a result, both the inserted board and the motherboard must have appropriate protection.
Regardless of the trend of miniaturization or high speed, there are unique problems. For example, high-current energy distribution is not a big issue for small, portable, handheld devices. And for desktops and servers, extended battery life won’t be an issue. However, latch-up and transient-induced damage are problems in both areas.

3.Lock-up and transient

Transients on deep sub-micron ICs from linewidths worsen the susceptibility to overvoltage conditions, which means you have to be smart about protecting these devices without compromising their performance.

In a protection input, any protection element must present a high impedance circuit under normal operation. It must be loaded with as little capacitance as possible, i.e. assuming it adds a small effect on the normal input signal. However, at the moment of overvoltage, that same device must become the primary path for that transient electrical energy, diverting it away from the input of the protected device. Also, the withstand voltage of the protection device should be higher than the maximum allowable voltage on the pin it protects. Similarly, its clamping voltage should be low enough to prevent damage to the protected device, because under transient conditions, the voltage on the input will be the clamping voltage of the protected device.
Previously, transient voltage suppression (TVS) diodes effectively clamped transients on printed circuit boards.

Traditional (TVS) diodes are solid-state PN junction devices and work well with voltages as low as 5V. They have fast response times, low clamping voltages, and high current surge capabilities – all desirable characteristics. However, the problem with conventional TVS diodes is that they rear their heads below 5V. Here, the avalanche technology they employ is an obstacle. To achieve a stand-off voltage below 5V, a high degree of doping (1018/cm-3 or above) is required. This, in turn, results in higher capacitance and leakage current, both of which compromise high performance. Conventional TVS diodes have a voltage-dependent capacitance that increases as voltage decreases. For example, at 5V, a typical ESD protection diode will have a junction capacitance of 400pF. We can imagine what problems would arise if such a capacitive load was added to the input node of a 100Base-TEthernet transmitter or receiver, or to the Universal Serial Bus (USB) input. Furthermore, these are exactly the types of circuits where transient protection is most needed.

Below 5V, traditional TVS diodes are not really an option. But that doesn’t mean you no longer have a choice. A new technology jointly developed by the University of California at Berkeley and Semtech Corporation (Newbury Park, California) provides transient and ESD protection down to an operating voltage of 2.8V. You can choose from a range of TVS devices with the appropriate capacitance, stand-off voltage, and clamping voltage to meet the requirements of your system. After that, you also have to consider where the device should be placed on the board, how to route the circuit board, etc.
Parasitic inductance in the protection path can cause high voltage overshoot and damage the IC. This is especially the case with fast rise time transients, such as ESD. The transient induced by ESD, according to the definition of IEC1000-4-2, will reach its peak value in less than 1 nanosecond (ns). Calculated based on the trace inductance of 20nH/inch, four 1-inch traces will cause an overshoot of 50V from a 10A pulse.

You must consider all possible sensing paths, including ground return paths, paths between the TVS and the guard circuit, and paths from the connector to the TVS device. Also, TVS devices should be placed as close to the connector as possible to couple transients to other nearby traces.

A 10/100Ethernet board is a subsystem that requires transient protection. Devices used in Ethernet switches and routers are exposed to high-energy, lightning-induced transients. The deep sub-micron IC used is extremely sensitive to over-voltage lock-in by design. In a typical system, the twisted pair interface used by each port consists of two different signal pairs – one pair for the transmitter and the other for the receiver. The transmitter input is usually the most susceptible to damage, with differential fatal discharges occurring within a line pair and capacitively coupling to the Ethernet IC through the transformer.

In one case, the signal frequency is very high (100Mbit/s) and the supply voltage is low (typically 3.3V). The protection device must have a very low capacitive load, and its stand-off voltage is much lower than 5V. There is another situation where parasitic inductance in the protection path can cause large voltage overshoot. To maximize efficiency, the circuit board should be laid out in such a way that the path between the protector and the protected circuit must be minimized, and the length of the path between the RJ45 connector and the protector must also be minimized.

4.Hot swap/plug and play

Increasingly, systems are designed to allow power strips or plugs to be plugged in and out at any time while the system is still powered. Those strips or plugs plug into and out of sockets with their own signal, power and ground wires and have a high chance of generating transients. Additionally, the system is able to dynamically adjust its power supply to accommodate sudden increases or decreases in current load.

Cell phones or other portable electronic devices can inadvertently be plugged into or unplugged from self-charging systems while power is on.

This also creates transients. Here, in addition to transient protection, there is also a need for energy management to accommodate sudden increases or decreases in current loads.
The USB interface is designed to improve high-speed serial interface capabilities between desktop systems and peripheral devices. Also, the UB interface has a voltage power supply line that can be used to power connected peripheral devices.

If there is no load plugged into the USB socket, it is an open socket. The ESD pulse discharge induced by the human body’s static electricity on the socket will be conducted to the circuit board and can easily damage the USB controller.

You have to make sure that in this high-speed bus, both the data lines and the power lines are protected. And, although energy management has been written into the USB specification, ESD protection has not.
TVS devices can be used to provide appropriate ESD protection. Component placement and via length remain important design issues. The same layout guidelines should be followed carefully. Make sure the path between the TVS and the protected line is short, and make sure the TVS device is as close as possible to the port connector.
According to the needs of USB specifications, solid circuit energy distribution switches should be used for energy management. In the PC host, they provide short-circuit current protection and error reporting to the controller IC. In USB peripherals, they are used for port switching, error reporting, and supply voltage ramp control.

5.Energy distribution

If you compare the change in PC current flow with that of 10 years ago, the magnitude of the increase is truly astonishing. Coupled with the substantial increase in clock frequency, PCs and servers are under extremely high di/dt environment. For example, if L is 2.5µH and C equals 4 x 1500µF, the transient on the load is of the order of 200mV peak-to-peak with a recovery time of 50 microseconds. Compounding the problem is putting the CPU into a mode such as sleep and then waking it up quickly, creating transients in the range of 20 to 30A per microsecond, thus becoming an energy management headache.
From a converter point of view, the value of di/dt governs the choice of the output capacitor, and more specifically the equivalent series resistance (ESR) and equivalent series inductance (ESL) of the capacitor. Converters operating at low frequencies require a large capacitance to store charge between two working cycles, which requires the use of electrolytic capacitors. Although these electrolytic capacitors have large capacitance, they also have large ESR and ESL, both of which are contrary to the designer’s intentions. In addition, electrolytic capacitors are large and unsuitable for surface mount technology and compact packaging.

There is an alternative way to reduce the values ​​of ESR and ESL, simplify the production process, and reduce the actual volume. The method is to use a slightly higher frequency converter, you can choose ceramic capacitors instead of electrolytic capacitors, and get the above advantages. At the same time, by using a multi-phase converter solution, you can share the load demand. Each converter requires less input capacitance while providing the same total current capability. Another advantage is reduced input ripple current. In a single-phase conversion scheme, the input ripple current is equal to half the output ripple current. Therefore, for a 20A system, the input ripple current is 10A. However, for a four-phase converter scheme, for example, this output current is divided equally among the four converters. Now each supplies 5A and their input ripple current is 2A. This allows for smaller, cheaper inputs capacitor.

6.Dell Computers (Round Rock, Texas) has developed a discrete, multiphase pulse-width modulation (PWM) controller and inverse DC-to-DC converter for its line of high-speed computers and servers.

It is designed to meet the urgent power/energy management requirements of Intel’s advanced Pentium CPU. The circuit has since been integrated by Semtech at Dell’s request. After adopting the multi-phase controller and converter solution, you need to pay special attention to the wiring of the circuit board. High-current switching at high frequencies will affect the voltage difference on the ground plane.

7.the high-current parts of the circuit should be routed first, and you should use a groundplate, or you should introduce an isolated or semi-isolated ground plane area to limit the ground current from entering a specific area. The loop formed by the input capacitor and the high-side and low-side driver output FETs contains all the high-current, fast-transient switching. Connections should be as wide as possible and as short as possible to reduce loop inductance. Doing so reduces electromagnetic interference (EMI), reduces ground-injected current, and minimizes source ringing for more reliable gate switching signals.

8.The connection between the two FET junctions and the output inductor should be a wide trace while being as short as possible.

The output capacitor should be placed as close to the load as possible. The fast transient load current is supplied by this capacitor, so the connecting traces should be wide and short to minimize inductance and resistance.

9.It is best to place the controller within a quiet ground plane area to avoid pulse currents in the input capacitor and FET loops from flowing into this area.

The high and low side ground reference pins should be returned to ground very close to the control amplifier package. The small signal analog ground and digital ground should be connected to the ground terminal of one of the output capacitors. Never return to ground inside the input capacitor/FET loop. The current sensing resistor loop should be kept as short as possible.

10.Work smart

While the above examples illustrate some ways to anticipate and avoid certain pitfalls of mixed-signal systems, they are by no means exhaustive. Each system has its own challenges, and each designer has its own unique hurdles to jump. Whether dealing with more difficult protection or tighter energy management, choosing the right components is the first step. There is a wide range of choices when it comes to challenge converters, converter controllers and TVS protection devices. Placing them in the right place on the circuit board can make all the difference in effective energy management and protection. Thoughtful routing and ground plane placement is the third key issue. TVS for low voltage circuits

When the voltage is lower than 5V, the traditional PN junction TVS actually does not work at all. However, there is an enhanced punch-through diode (EPD) developed by the University of California, Berkeley and Semtech.

Different from the traditional PN structure of avalanche TVS diodes, this EPD device adopts a more complex n+p+p-n+ four-layer structure. It uses light doping in the p+ and P- layers to prevent the reverse-biased n+p+ junction from entering an avalanche state.
The npn structure was chosen over the pnp structure because of its higher electron mobility and improved clamping characteristics. By carefully constructing the P-base region, the resulting device achieves excellent leakage, clamping and capacitance characteristics in the voltage range of 2.8V to 3.3V.

11.Pentium with a huge appetite

Intel’s Pentium II specification requires the current to increase from 5A to 20A within 500ns, with a conversion rate of 30A per microsecond. The SemteckSC1144 polyphase PWM controller’s capabilities are more than the task requires. It provides control of up to four reverse DC-to-DC converters with the required speed and accuracy. The built-in 5-bit DAC allows the output voltage to be programmed from 1.8 to 2.05V in 50mV increments, and from 20 to 3.5V in 100mV increments.
This multiphase technology produces four precise output voltages separated by 90-degree phase shifts. These four digitally phase-shifted outputs are then summed together to obtain the required output voltage and current capabilities.
With each converter operating at 2MHz, designers can use ceramic capacitors instead of electrolytic capacitors and get the benefits of small size, surface mountability, and lower ESR and ESL.