Using wiring techniques to improve signal integrity of embedded system PCB
O Introduction
With the rapid development of electronic technology, embedded systems are increasingly used. In many applications, people no longer consider functions and performance, but reliability and compatibility. Printed circuit boards (PCBs) are the basic support for circuit elements and devices in electronic products. Their design quality often directly affects the reliability and compatibility of embedded systems.
In the past, in some low-speed circuit boards, the clock frequency was generally only about 10 MHz. The main challenge of circuit board or package design was how to route all signal lines on a double-layer board and how to avoid damaging the package during assembly. Since the interconnection lines have never affected the system performance, the electrical characteristics of the interconnection lines are not important. In this sense, the interconnection lines in the low-speed circuit board are smooth and transparent to the signal. However, with the development of embedded systems, the circuits used are basically high-frequency circuits.
As the clock frequency increases, the rising edge of the signal also becomes shorter.
The capacitive reactance and inductive reactance generated by the printed circuit to the passing signal will be much greater than the resistance of the printed circuit itself, which seriously affects the integrity of the signal. For embedded systems, when the clock frequency exceeds 100 MHz or the rising edge is less than 1 ns, the signal integrity effect becomes important.
In PCB, signal line is the main carrier of signal transmission.
The routing of signal line will directly determine the superiority of signal transmission, thus directly affecting the performance of the whole system. Unreasonable wiring will seriously cause a variety of signal integrity problems, generate timing, noise and electromagnetic interference (EMI) to the circuit, which will seriously affect the performance of the system. In this regard, this paper starts from the actual electrical characteristics of signal lines in high-speed digital circuits, establishes electrical characteristics model, finds the main reasons affecting signal integrity and solutions to the problems, and gives the problems that should be paid attention to in wiring and the methods and techniques to follow.
1 Signal integrity
Signal integrity refers to the quality of the signal on the signal line, that is, the ability of the signal to respond with the correct timing and voltage level in the circuit. The signal has good signal integrity, which means that it has the necessary voltage level value when needed. Poor signal integrity is not caused by a single factor, but by multiple factors in board-level design. Signal integrity problems are reflected in many aspects, mainly including delay, reflection, crosstalk, overshoot, oscillation, ground bounce, etc.
Delay: Delay refers to the transmission of signals at a limited speed on the transmission line of the PCB board. There is a transmission delay between the signal from the transmitter and the receiver. Signal delay will affect the timing of the system; the transmission delay mainly depends on the length of the wire and the dielectric constant of the medium around the wire. In high-speed digital systems, the length of the signal transmission line is the most direct factor affecting the clock pulse phase difference. The clock pulse phase difference refers to the time when two clock signals generated at the same time arrive at the receiving end. The clock pulse phase difference reduces the predictability of the arrival of the signal edge. If the clock pulse phase difference is too large, an erroneous signal will be generated at the receiving end.
Reflection: Reflection is the echo of the signal on the signal line. When the signal delay time is much longer than the signal jump time, the signal line must be treated as a transmission line.
When the characteristic impedance of the transmission line does not match the load impedance, part of the signal power (voltage or current) is transmitted to the line and reaches the load, but part of it is reflected. If the load impedance is less than the original impedance, the reflection is negative; otherwise, the reflection is positive. Changes in wiring geometry, incorrect wire termination, transmission through connectors, and power plane discontinuities can all lead to such reflections.
Crosstalk: Crosstalk is the coupling between two signal lines, the mutual inductance and mutual capacitance between signal lines causing noise on the signal line. Capacitive coupling causes coupling current, while inductive coupling causes coupling voltage. Crosstalk noise originates from electromagnetic coupling between signal line nets, between signal systems and power distribution systems, and between vias.
Crosstalk may cause false clocks, intermittent data errors, etc., affecting the transmission quality of adjacent signals. In reality, crosstalk cannot be completely eliminated, but it can be controlled within the range that the system can withstand. PCB board layer parameters, signal line spacing, electrical characteristics of the driver and receiver, and baseline termination methods all have a certain impact on crosstalk.
Overshoot and undershoot: Overshoot is the first peak or valley value exceeding the set voltage. For the rising edge, it refers to the highest voltage; for the falling edge, it refers to the lowest voltage. Undershoot is the next valley or peak value exceeding the set voltage. Excessive overshoot can cause the protection diode to work, resulting in its premature failure. Excessive undershoot can cause false clock or data errors (misoperation).
Ringing and rounding: The oscillation phenomenon is repeated overshoot and undershoot. Signal oscillation is caused by the inductance and capacitance of the transition on the line, which is an underdamped state, while rounding is an overdamped state. Oscillation and rounding are caused by many factors like reflection. Oscillation can be reduced by proper termination, but it is impossible to completely eliminate it.
Ground bounce noise and reflux noise: bit will cause ground bounce noise. For example, when the outputs of a large number of chips are turned on at the same time, a large transient current will flow through the power plane of the chip and the board. The inductance and resistance of the chip package and the power plane will cause power supply noise, which will cause voltage fluctuations and changes on the real ground plane. This noise will affect the operation of other components. The increase in load capacitance, the decrease in load resistance, the increase in ground inductance, and the increase in the number of switching devices will all lead to an increase in ground bounce.
2 Analysis of electrical characteristics of transmission channels
In multi-layer PCBs, most transmission lines are not only arranged on a single layer, but are staggered on multiple layers, and the layers are connected through vias. Therefore, in a multi-layer PCB, a typical transmission channel mainly includes three parts: transmission lines, routing corners, and vias. In low-frequency conditions, printed lines and routing vias can be regarded as ordinary electrical connections connecting different device pins, which will not have much impact on signal quality. However, in high-frequency conditions, printed lines, corners, and vias cannot only consider their connectivity, but also the influence of their electrical characteristics and parasitic parameters at high frequencies.
2.1 Analysis of the electrical characteristics of transmission lines in high-speed PCBs
In high-speed PCB design,
it is inevitable to use a large number of signal connection lines of different lengths. The delay time of the signal passing through the connection line cannot be ignored compared with the change time of the signal itself. The signal is transmitted on the connection line at the speed of electromagnetic waves. At this time, the connection line is a complex network with resistance, capacitance, and inductance, which needs to be described by a distributed parameter system model, that is, a transmission line model. The transmission line is used to transmit the signal from one end to the other end. It consists of two wires of a certain length, one is called the signal path and the other is called the return path.
In low-frequency circuits, the characteristics of the transmission line are pure resistance electrical characteristics. In high-speed PCBs, as the frequency of the transmission signal increases, the capacitive impedance between the wires decreases, and the inductive impedance on the wire increases. The signal line will no longer only show pure resistance, that is, the signal will not only be transmitted on the wire, but also in the medium between the conductors. If the signal frequency increases further, when jωL>>R, 1/(jωC)<<R, the inductive reactance jωL and the capacitive reactance 1/(jωC) on the wire become more important factors than the resistance R. Figure 1 is an equivalent model of the electrical characteristics of the transmission line.
For uniform conductors, without considering changes in the external environment, the resistance R, the parasitic inductance L of the transmission line and the parasitic capacitance C are evenly distributed (i.e., L1=L2=…=Ln; C1=C2=…=Cn+1). Assuming that the transmission line is a lossless transmission line, that is, when R=0, if the line parameters are taken: the capacitance per unit length C1, the inductance per unit length L1 and the total length of the transmission line is Len, then:
Total capacitance of the transmission line:
Total inductance of the transmission line:
According to the line parameters and total length of the transmission line, the characteristic impedance Z0 and the delay TD of the transmission line can be calculated, and the formula is as follows:
It can be clearly seen from the above formula that increasing the capacitance and reducing the inductance can reduce the characteristic impedance; reducing the total length of the transmission line, as well as the capacitance and inductance, can reduce the transmission delay on the signal line.
2.2 Electrical characteristics analysis of vias in high-speed PCBs
A via usually refers to a hole in a printed circuit board, which is an important factor in the design of multi-layer PCBs. Vias can be used to fix and install plug-in components or connect the wiring between layers. From the process level, vias are generally divided into three categories: blind vias, buried vias and through holes. Blind vias are located on the top and bottom surfaces of printed circuit boards, have a certain depth, and are used to connect the surface circuits with the inner circuits below. The depth and diameter of the hole usually do not exceed a certain ratio.
Buried vias are connection holes located on the inner layer of printed circuit boards, which do not extend to the surface of the circuit board.
Through holes pass through the entire circuit board and can be used to interconnect inter-layer wiring or as mounting positioning holes for components. Since through holes are easier to implement in terms of process and have lower costs, through holes are generally used in printed circuit boards instead of the other two types of vias. The vias mentioned below are all considered as through holes.
As a special transmission line, in high-speed circuits, vias not only generate parasitic capacitance to the ground, but also parasitic inductance. The equivalent model of its electrical characteristics is shown in Figure 2.
The parasitic capacitance of vias mainly affects the circuit by slowing down or deteriorating the rising edge of digital signals, reducing the speed of the circuit
. The smaller the parasitic capacitance value of the via, the smaller the impact. If the diameter of the isolation hole of the via on the bottom layer is DG, the diameter of the via pad is Dv, the thickness of the PCB is H, and the dielectric constant of the substrate material is ε, then the size of the parasitic capacitance C of the via is approximately:
The main impact of the parasitic inductance of the via is to reduce the effectiveness of the power bypass capacitor and make the entire power supply filtering effect worse. If L is the parasitic inductance of the via, h is the length of the via, and DH is the diameter of the center drill hole, the following formula can be used to simply calculate the parasitic inductance of a via:
From the above formula, it can be seen that the via diameter has a small impact on the inductance, and the via length has a greater impact on the inductance. In PCB, one end of the bypass capacitor is usually connected to the ground plane through a through hole, and the other end is also connected to the power plane through a through hole, so the impact of the through hole inductance will increase by 1 times.
2.3 Contribution of transmission line corners to the signal integrity problem of the transmission channel
When the signal propagates along a uniform connection line, no reflection and transmission signal distortion will occur. However, the corners on the transmission line will change the impedance at the transmission line, causing partial reflection and distortion of the signal. According to the capacitance per unit length of the wire C1 (unit: pF/in) and the wire width ω (unit: in), the parasitic capacitance Ccorner of each corner can be simply estimated by the following formula:
When the signal line width is narrow in a high-density circuit board, the accumulated delay caused by the parasitic capacitance at the corner is generally unlikely to have a significant impact on signal integrity. However, for high-frequency sensitive circuits, such as high-frequency clock lines, the cumulative effect of corner parasitic capacitance should be considered.
3 Use wiring techniques to suppress signal integrity issues
When the signal is output from the driving source, the current and voltage that constitute the signal regard the interconnect as an impedance network. As the signal propagates along the impedance network, it continuously senses the transient impedance changes caused by the interconnect. If the impedance sensed by the signal remains unchanged, the signal is not distorted.
Once the impedance changes, the signal will be reflected at the change point and distorted when passing through the rest of the interconnect. If the impedance change is large enough, the distortion will cause false triggering. In the process of signal integrity optimization design, an important design goal is to design all interconnects into uniform transmission lines and reduce the length of all non-uniform transmission lines so that the impedance felt by the signal in the entire network remains unchanged.
Based on this, some methods of using wiring techniques to suppress signal integrity problems can be summarized:
the routing shape of printed conductors should not be tangled, branched or hard corners, and T-shaped lines and pile lines should be avoided as much as possible; the line width of the signal line in the same network should be kept as much as possible to reduce the line width change; reduce the length of the transmission line and increase the wire width; try to increase the distance between the wires; minimize the vias and corners of high-speed signal lines and reduce the inter-layer conversion of signal lines; reasonably select the size of the vias; reduce the signal loop area and loop current. In short, any feature that changes the cross-section or network geometry will change the impedance felt by the signal. The key to reducing signal integrity problems in wiring is to reduce the impedance mutation on the transmission line so that the impedance felt by the signal in the entire network remains unchanged.
4 Conclusion
With the development of embedded systems, signal integrity has become an extremely important content in the PCB design of embedded systems, affecting the success or failure of the entire PCB design. When the circuit is determined, the components are selected, and the PCB layout is determined, wiring techniques can be used to suppress the occurrence of signal integrity problems, improve the reliability of the PCB, and minimize the losses caused by signal integrity problems.
