EMC Design Strategy—–PCB Design
I. Layout of Devices
In the process of PCB design, from the perspective of EMC, three main factors should be considered first: the number of input/output pins, device density and power consumption. A practical rule is that the area occupied by sheet components is 20% of the substrate, and the power dissipation per square inch is not more than 2W.
In terms of device layout, in principle, related devices should be placed as close as possible,
digital circuits, analog circuits and power circuits should be placed separately, and high-frequency circuits should be separated from low-frequency circuits. Devices that are prone to noise, small current circuits, large current circuits, etc. should be kept as far away from logic circuits as possible. The main interference and radiation sources such as clock circuits and high-frequency circuits should be arranged separately, away from sensitive circuits. Input and output chips should be located close to the I/O exit of the hybrid circuit package.
High-frequency components should shorten the connection as much as possible to reduce distributed parameters and mutual electromagnetic interference.
Susceptible components should not be too close to each other, and input and output should be kept as far away as possible. The oscillator should be as close as possible to the location where the clock chip is used, and away from the signal interface and low-level signal chip. Components should be arranged parallel or perpendicular to one side of the substrate, and components should be arranged in parallel as much as possible. This will not only reduce the distributed parameters between components, but also conform to the manufacturing process of the hybrid circuit and be easy to produce.
On the hybrid circuit substrate, the lead pads of the power supply and ground should be arranged symmetrically, and it is best to evenly distribute many power supply and ground I/O connections. The mounting area of the bare chip is connected to the most negative potential plane.
When selecting a multi-layer hybrid circuit, the interlayer arrangement of the circuit board changes with the specific circuit, but generally has the following characteristics.
(1) The power supply and ground laye
s are allocated in the inner layer, which can be regarded as shielding layers. They can effectively suppress the common-mode RF interference inherent in the circuit board and reduce the distributed impedance of the high-frequency power supply.
(2) The power plane and ground plane in the board are as close to each other as possible. Generally, the ground plane is above the power plane.
In this way, the interlayer capacitance can be used as the smoothing capacitance of the power supply. At the same time, the ground plane plays a shielding role for the radiation current distributed on the power plane.
(3) The wiring layer should be arranged as close to the power or ground plane as possible to produce a flux cancellation effect.
2.PCB routing
In circuit design, people often only focus on improving wiring density or pursuing uniform layout, ignoring the impact of line layout on preventing interference, causing a large number of signals to radiate into space to form interference, which may lead to more electromagnetic compatibility problems. Therefore, good wiring is the key to determining the success of the design.
3.Ground wire layout
The ground wire is not only the potential reference point for the circuit operation, but also can be used as a low-impedance loop for the signal. The most common interference on the ground wire is the ground loop interference caused by the ground loop current. Solving this type of interference problem is equivalent to solving most of the electromagnetic compatibility problems.
The noise on the ground wire mainly affects the ground level of the digital circuit, and when the digital circuit outputs a low level, it is more sensitive to the noise of the ground wire. The interference on the ground wire may not only cause the circuit to malfunction, but also cause conduction and radiation errors. Therefore, the key to reducing these interferences is to reduce the impedance of the ground wire as much as possible (for digital circuits, reducing the ground wire inductance is particularly important).
Pay attention to the following points when laying out the ground wire:
(1) According to different power supply voltages, set ground wires for digital circuits and analog circuits respectively.
(2) Make the public ground wire as thick as possible. When using multi-layer thick film technology, a ground plane can be specially set up, which helps to reduce the loop area and also reduces the efficiency of the receiving antenna. It can also serve as a shield for the signal line.
(3) Comb-shaped ground lines should be avoided. This structure makes the signal return loop very large, which will increase radiation and sensitivity, and the common impedance between chips may also cause circuit malfunction.
(4) When multiple chips are installed on the board, there will be a large potential difference on the ground line. The ground line should be designed as a closed loop to improve the noise tolerance of the circuit.
(5) For circuit boards with both analog and digital functions, the analog ground and digital ground are usually separated and only connected at the power supply.
- Layout of power lines
Generally speaking, in addition to interference caused directly by electromagnetic radiation, electromagnetic interference caused by power lines is the most common. Therefore, the layout of the power line is also very important, and the following rules should usually be followed.
(1) The power line should be as close to the ground line as possible to reduce the power supply loop area, reduce differential mode radiation, and help reduce circuit interference. The power supply loops of different power supplies should not overlap with each other.
(2) When using multi-layer technology, separate the analog power supply and the digital power supply to avoid mutual interference. Do not overlap the digital power supply with the analog power supply, otherwise coupling capacitance will be generated, destroying the separation.
(3) The power plane and the ground plane can be completely isolated by dielectric. When the frequency and speed are very high, a dielectric slurry with a low dielectric constant should be used. The power plane should be close to the ground plane and arranged under the ground plane to shield the radiation current distributed on the power plane.
(4) The power pin and the ground pin of the chip should be decoupled. The decoupling capacitor uses a 0.01uF chip capacitor and should be installed close to the chip to minimize the loop area of the decoupling capacitor.
(5) When using a surface-mount chip, try to use a chip with a power pin and a ground pin close to each other, which can further reduce the power supply loop area of the decoupling capacitor and help achieve electromagnetic compatibility.
3.Layout of signal lines
When using a single-layer film process, a simple and applicable method is to lay out the ground line first, then lay out the key signals, such as high-speed clock signals or sensitive circuits close to their ground loops, and finally lay out other circuits. The layout of the signal line is best arranged according to the flow order of the signal, so that the signal on the circuit board flows smoothly.
If you want to minimize EMI, keep the signal line as close as possible to the return signal line it forms, and make the loop area as small as possible to avoid radiation interference. Low-level signal channels cannot be close to high-level signal channels and unfiltered power lines, and noise-sensitive wiring should not be parallel to high-current and high-speed switching lines.
If possible, lay out all key routing lines in strip lines. Incompatible signal lines (digital and analog, high-speed and low-speed, high-current and low-current, high-voltage and low-voltage, etc.) should be kept away from each other and not run in parallel. Crosstalk between signals is extremely sensitive to the length and spacing of adjacent parallel lines, so try to increase the spacing between high-speed signal lines and other parallel signal lines and reduce the parallel length.
The inductance of the conductive strip is proportional to its length and the logarithm of its length, and inversely proportional to the logarithm of its width.
Therefore, the conductive strip should be as short as possible, and the length of each address line or data line of the same component should be kept consistent as much as possible. The wires used as circuit input and output should avoid being parallel to each other as much as possible. It is best to add a ground wire between them to effectively suppress crosstalk. The wiring density of low-speed signals can be relatively large, and the wiring density of high-speed signals should be as small as possible.
In the multi-layer thick film process, in addition to complying with the rules of single-layer wiring, it should also be noted that:
Try to design a separate ground plane, and arrange the signal layer adjacent to the ground layer. When it cannot be used, a ground wire must be set near the high-frequency or sensitive circuit. The signal lines distributed on different layers should be perpendicular to each other, so as to reduce the electric field and magnetic field coupling interference between the lines; the signal lines on the same layer should maintain a certain distance, and it is best to isolate them with the corresponding ground wire loop to reduce the signal crosstalk between the lines. Each high-speed signal line should be limited to the same layer
. The signal line should not be too close to the edge of the substrate, otherwise it will cause the characteristic impedance to change, and it is easy to generate edge fields and increase outward radiation.
4.Layout of clock circuits
Clock circuits play an important role in digital circuits and are also the main source of electromagnetic radiation. The spectrum of radiation energy of a clock signal with a 2ns rising edge can reach 160MHz. Therefore, designing a good clock circuit is the key to ensuring electromagnetic compatibility of the entire circuit. Regarding the layout of the clock circuit, there are the following points to note:
(1) Do not use a daisy chain structure to transmit clock signals, but a star structure, that is, all clock loads are directly connected to the clock power driver.
(2) All conduction bands connected to the input/output ends of the crystal oscillator should be as short as possible to reduce noise interference and the influence of distributed capacitance on the crystal oscillator.
(3) The ground wire of the crystal oscillator capacitor should be connected to the device using a conduction band as wide and short as possible; the digital ground pin closest to the crystal oscillator should have as few vias as possible.
III. Selection of processes and components
There are three manufacturing processes available for hybrid integrated circuits: single-layer thin film, multi-layer thick film, and multi-layer co-fired thick film. Thin film technology can produce small-size, low-power and high-current density components required for high-density hybrid circuits. It has the characteristics of high quality, stability, reliability and flexibility, and is suitable for high-speed, high-frequency and high-packaging density circuits.
However, it can only do single-layer wiring and the cost is relatively high.
Multilayer thick film technology can manufacture multi-layer interconnected circuits at a lower cost. From the perspective of electromagnetic compatibility, multilayer wiring can reduce the electromagnetic radiation of the circuit board and improve the anti-interference ability of the circuit board. Because a special power layer and ground layer can be set up, the distance between the signal and the ground wire is only the distance between the layers. In this way, the loop area of all signals on the board can be minimized, thereby effectively reducing differential mode radiation.
Among them, the multilayer co-fired thick film process has more advantages and is the mainstream technology of passive integration. It can realize more layers of wiring, easy to embed components, improve assembly density, and has good high-frequency characteristics and high-speed transmission characteristics. In addition, it has good compatibility with thin film technology. The combination of the two can achieve hybrid multilayer circuits with higher assembly density and better performance.
Active devices in hybrid circuits are generally bare chips. If bare chips are not available, corresponding packaged chips can be used. To obtain the best EMC characteristics, surface-mount chips should be used as much as possible. When selecting chips, low-speed clocks should be used as much as possible on the premise of meeting product technical indicators. Never use AC when HC can be used, and do not use HC if CMOS4000 can be used. Capacitors should have low equivalent series resistance to avoid large attenuation of signals.
The packaging of hybrid circuits can use Kovar metal bases and shell covers, parallel seam welding, which has a good shielding effect.
