Key technologies and progress in high-speed and high-density PCB design

High-speed and high-density have gradually become one of the significant development trends of many modern electronic products, and high-speed and high-density PCB design technology has become an important research field.

Compared with traditional PCB design, high-speed and high-density PCB design has several key technical issues, which require the development of new design technologies, and there are many theoretical and technical issues that need to be studied in depth. At the same time, the requirements for high-speed and high-density PCBs are getting higher and higher, which makes high-speed and high-density PCB design constantly face new problems; the continuous emergence of a large number of related research results has promoted the continuous development of high-speed and high-density PCB design technology. This article introduces the key technical issues of high-speed and high-density PCB design (signal integrity, power integrity, EMC/EM I and thermal analysis) and the new progress of related EDA technology, and discusses several important trends in high-speed and high-density PCB design.

Key technical issues

The key technical issues of high-speed and high-density PCB design mainly include signal integrity (signal integrity, SI), power integrity (power integrity, PI), EMC/EM I and thermal analysis.

Signal integrity

Signal integrity mainly refers to the quality of signal transmission on the signal line. When the circuit signal can reach the pin of the receiving chip with the required timing, duration and voltage amplitude, the circuit has good signal integrity. When the signal cannot respond normally or the signal quality cannot make the system work stably for a long time, a signal integrity problem occurs. Signal integrity problems are mainly manifested as: delay, reflection, overshoot, ringing, crosstalk, timing, synchronous switching noise, EMI, etc.

Signal integrity problems will directly lead to signal distortion, timing errors, and the generation of incorrect data, address and control signals, causing system errors or even paralysis. Usually, for digital chips, the level above V IH is logic 1, the level below V IL is logic 0, and the level between VIL ~ VIH is an uncertain state. For digital signals with ringing, when the oscillation level enters the uncertain area of ​​VIL ~ VIH, it may cause logical errors. The transmission of digital signals must have correct timing. General digital chips require that the data must be stable before tsetup of the clock trigger edge to ensure the correct timing of the logic. If the signal transmission delay is too long, the correct logic may not be received at the rising or falling edge of the clock, causing timing errors.

The causes of signal integrity problems are more complicated. The parameters of components, PCB parameters, layout of components on PCB, and wiring of high-speed signals are all important factors affecting signal integrity. Signal integrity is a system problem. Research and solution of signal integrity problems must be based on a system perspective.

Relatively speaking, people have studied signal integrity issues for decades, achieved many important theoretical and technical results, and accumulated rich experience. Many signal integrity technologies are relatively mature and have been widely used.

Power integrity

Power integrity mainly refers to the fact that in high-speed systems, the impedance characteristics of the power distribution system (PDS) are different at different frequencies, so that the voltage between the power layer and the ground layer on the PCB is different at different places on the circuit board, resulting in discontinuous power supply, power noise, and chip failure. At the same time, due to high-frequency radiation, power integrity problems will also bring EMC/EM I problems. In high-speed, low-voltage circuits, the harm of power noise is particularly serious.

The proposal of power integrity stems from the huge errors caused by signal integrity analysis based on wiring and device models without considering the influence of power supply.

Relatively speaking, the research on power integrity started late, and the theoretical research and technical means are not mature enough. It is one of the biggest challenges in high-speed and high-density PCB design. At present, some common measures are mainly taken to minimize the adverse effects caused by power integrity problems to a certain extent. The main measures taken are: first, optimize the stacking, layout and wiring design of PCB; second, appropriately increase the decoupling capacitor. When the system frequency is less than 300-400 MHz, setting a suitable capacitor at an appropriate position can help reduce the impact of power integrity problems. However, when the system frequency is higher, the role of decoupling capacitors is small. In this case, the impact of power integrity problems can only be reduced by optimizing PCB design.

EMC

EMC (electromagnetic compatibility) is usually defined as: “the ability of a device or system to work normally in its electromagnetic environment and not cause unbearable electromagnetic interference to anything in the environment.” Some define it as: “It is a science that studies how various electrical equipment (subsystems, systems, and in a broad sense, organisms) can coexist without causing degradation under limited space, limited time and limited spectrum resources.”

EMC mainly studies EMI (electromagnetic interference) and EMS (electromagnetic susceptibility). EMI is caused by the electromagnetic interference source transferring energy to the sensitive system through the coupling path. It includes three basic forms: conduction by wires and common ground wires, radiation through space, or coupling through near fields.

EMC of electronic products is very important.

At present, many countries and regions have strict and complete EMC standards. More and more electronic products must pass relevant EMC testing and certification before entering the market. Moreover, with the deterioration of the electromagnetic environment, the EMC requirements for electronic products will become higher and higher.

Relatively speaking, EMC issues are the most complex.

When the rise time or fall time is reduced from 5 ns to 2.5 ns, the EMI will increase by about 4 times. The spectrum width of the EMI is inversely proportional to the rise time1, and the radiation intensity of the EMI is proportional to the square of the frequency1. The frequency range of this type of EMI radiation is about tens of MHz to several GHz. The wavelengths corresponding to these high frequencies are very short. Short connecting wires on the PCB or even the interconnects within the chip may become efficient transmitting or receiving antennas, thereby causing serious EMC problems. Henry W Ott, president of Henry Ott Consulting, emphasized in his keynote speech at the PCB Design Conference-East: “In the era of high-speed design, PCB designers will face many unexpected problems if they do not know more about EMC issues.” “EMC will become a greater challenge as design speeds are faster and wireless design has become more and more common.”

Due to the complexity of EMC and the increasing requirements of modern electronic products for EMC, EMC technology will be an important field that requires long-term research. At present, the prevention and solution of EMC problems mainly follow some common PCB design constraint rules, but the specific rules adopted and the effect must be analyzed according to the specific problems, which depends largely on the theoretical level and practical experience of the designer.

Thermal analysis

The dynamic power consumption of widely used CMOS digital chips increases with the increase of working speed, such as the dynamic power consumption Pdyn = CLV2DDf0→1 of CMOS inverters. Due to the skin effect, the effective conductive cross-sectional area of ​​the connecting wire decreases with the increase of frequency, causing the resistance of the connecting wire to increase with the increase of frequency (Rac∝ f). The connecting wire also has inductance, and the inductive reactance (2πfL) also increases with the increase of frequency. The impedance of the connecting wire can be regarded as the series connection of the two.

It can be seen that the power consumption of the connecting wire also increases with the increase of working speed. The increase of power consumption means the increase of heat. The high-density pin packaging and miniaturized packaging of components, as well as the increase of component density on PCB, all make the heat dissipation conditions worse. These factors can cause the PCB temperature to be too high.

Electronic components have a specified operating temperature range.

Rising temperatures can cause component performance degradation and premature failure. Excessive temperatures can burn out components, PCB traces, vias, etc. Therefore, thermal analysis of high-speed and high-density PCBs is also very important. Through thermal analysis, the thermal field distribution of the PCB, the temperature of components and solder joints, and the potential heat dissipation and reliability problems in PCB design can be determined, so that necessary measures can be taken in a targeted manner.

The thermal analysis of high-speed and high-density PCBs involves many complex factors such as heat transfer theory, thermal models of components, layout of components, circuit working modes (such as static and dynamic), natural and artificial heat dissipation measures, so this work is difficult to be completed manually. Although some EDA tools have thermal analysis functions, they are far from meeting the needs of high-speed and high-density PCB design.

By the way, signal integrity, power integrity, EMC/EM I and other issues in high-speed and high-density PCBs affect and restrict each other. In the PCB design process, these issues need to be considered comprehensively.

New progress in related EDA technology

From the key technical issues of high-speed and high-density PCB, it can be seen that traditional PCB design methods can no longer meet the needs of high-speed and high-density PCB design. According to experts, “To design a high-speed system, we must first have a strong high-speed design concept and high-speed design theory, a standardized design process, and use advanced high-speed design tools to conduct sufficient pre-analysis, obtain certain constraint rules, strictly follow the rules to drive layout and routing, and strictly perform post-simulation verification to ensure the accuracy of the design. Repeated practice of this design process can continuously improve the design skills in the field of high-speed design.

” It can be seen that for high-speed and high-density PCB design, in addition to having the necessary theoretical knowledge and practical experience, the help of advanced EDA tools is crucial. Using the simulation function of EDA tools, we can judge whether the function is correct and how the performance is; we can judge whether the direction of improvement is correct and how the effect is; we can compare and select different solutions.

For high-speed and high-density PCB design, from schematic design to PCB design, it is generally completed with the help of EDA tools. Currently popular EDA tools include Protel, PADS, OrCAD, Cadence, Mentor, etc. These EDA tools have their own characteristics, and their functions and usage can be found in many documents and websites. Some EDA tools support PCB simulation to varying degrees, including signal integrity simulation, electromagnetic interference simulation, thermal simulation, etc. Cadence, Mentor, etc. have been more successful in PCB signal integrity and electromagnetic interference simulation; FLOTHERM, Auto Therm, BETAsoft, Quick Thermal, etc. have been more successful in PCB thermal simulation. The following mainly introduces the new progress of these simulation functions.

For signal integrity simulation, Cadence’s SpectraQuest is a good simulation tool.

It can be used to model and simulate in the early stage of design, so as to form constraint rules to guide the later layout and routing, and improve design efficiency. Cadence launched the MGH simulator specifically for 1000 MHz in June 2004, which can complete the simulation of tens of thousands of BIT 1000 MHz signals in a few seconds, making the simulation function more powerful.

Because power integrity is a new challenge, there are relatively few simulation tools at present.

According to reports, Cadence’s power integrity tool PI has been launched on the market and has been successfully applied to the designs of some customers.

At present, the simulation effect of EMC/EM I is the worst, mainly because of the complexity of EMC/EM I. At present, the main method of expert inspection is to convert EMC/EM I problems into layout and wiring rules on PCB according to international general standards. Cadence’s EMControl is such a rule checking tool similar to an expert system, and it also provides a customized interface to facilitate customers to write EMC/EM I inspection rules suitable for their own company. Mentor Graphics’ Quiet Expert can check the incorrect wiring structure that causes EMC I problems, find out the problems, and give the causes and suggested solutions to EMC I problems. In terms of three-dimensional analysis, Ansoft, Ap sim, etc. can provide specialized tools and methods, and these tools can be used in conjunction with Cadence and Mentor Graphics system tools.

FLOTHERM is a standard software for thermal analysis in the electronics industry. It is a thermal analysis software based on computational fluid dynamics (CFD). Thousands of companies around the world use FLOTHERM to exchange thermal models. Leading electronic component manufacturers provide their customers with FLOTHERM models of their products.

The Auto Therm board-level thermal analysis tool moves the thermal analysis of PCBs to the early stage of the design process, achieving a successful first-time PCB design and improving the reliability of PCBs. Auto Therm automatically generates a complete thermal model from the LAYOUT or Fablink database, speeding up the thermal definition of the circuit board, components and environment, and reducing the execution time of thermal analysis. The analysis results can be customized in the form of graphics, charts and reports. Using the what-if analysis method, by changing the boundary conditions, placing devices and adding heat sinks or fans, the board-level thermal distribution under different conditions can be quickly analyzed and proposed. Auto Therm can perform steady-state and transient conduction, convection and radiation analysis, and then study the transient effects of cooling failure and cyclic processes.

BETAsoft can easily determine potential heat dissipation and reliability problems in the design by determining the temperature and its gradient of the PCB, the temperature of components and solder joints

. Due to the use of the local variable step size finite element differential method, its calculation speed is greatly improved compared with the traditional finite element algorithm. For heat conduction, convection and radiation, BETAsoft can establish complex three-dimensional airflow and thermal field models, and consider whether heat sinks, chip fans, thermal pads and other heat dissipation devices are installed on the components. The error between BETAsoft’s analysis results and actual measurement results can reach less than 10%.

Quick Thermal can realize online real-time thermal analysis of PCB design, and can quickly, flexibly and conveniently evaluate the thermal state of PCB. It has flexible thermal analysis environment setting and component property setting functions for quick compromise. It has intuitive real-time isothermal diagram result display, alarm display and other functions. In addition, Altium’s Protel 2004 has also been significantly enhanced in simulation functions.

Several development trends

Chip design, package design and PCB board-level design are inseparable

For the design process on the silicon chip, it is necessary to consider the use of a suitable package to match the PCB. The overall layout of the chip design is not only limited by the process, but also takes into account many constraints at the PCB board level. Where must be consideredThere will be signal discontinuity, where will the matching problem appear. For the chip package, matching with PCB is one aspect, and more importantly, the appropriate package selection is very helpful in solving the signal integrity, EMC/EM I and other problems at the PCB board level. For example, some timing problems that are difficult to solve on PCB are easy to solve in the package.

The new package design is to reduce the parasitic parameters of the chip, thereby weakening the parasitic effects.

The parasitic effects of the chip include ground bounce and noise, propagation delay, edge rate, frequency response, output lead lag, antenna effect, etc. The new package design mainly includes multiple ground and power pins, short leads, and a layout that minimizes capacitive coupling between pins. The new package design has a significant effect on improving EMC performance. For example, the DQFN package has a smaller lead frame and uses package welding terminals instead of external leads, which greatly reduces the length of the package connection wires and related parasitic parameters. Compared with the TSSOP package, the DQFN package connection length is reduced by more than 50%.

Therefore, for high-speed and high-density PCB design, chip design, package design and PCB board-level design are becoming increasingly inseparable, requiring designers to consider Silicon-Package-Board design at the same time and coordinate the relationship between them. This is also a major problem that EDA manufacturers need to face for a long time.

Cadence is a leader in system-level process design.

Its Allegro platform covers both board-level design and package-level design, and can be connected in series with several other chip design platforms of Cadence to form a complete design chain and achieve effective data exchange and communication. In addition, Cadence’s VSIC (virtual system interconnect) design method is a new Silicon-Package-Board collaborative design method, which enables designers to consider the timing or signal integrity problems caused by the entire system in the early stages of design, solving a major problem in 1,000 MHz signal design.

The role of EDA tools is becoming increasingly important

On the one hand, as far as the key technical issues of high-speed and high-density PCB are concerned, the perfect solution of any of them cannot be separated from the help of EDA tools. On the other hand, the increasingly high requirements for high-speed and high-density PCBs, in turn, prompt EDA manufacturers to continuously develop better EDA tools. The two form a virtuous circle and the relationship is getting closer and closer. It is certain that in high-speed and high-density PCB design, the role of EDA tools is becoming more and more important. For designers, timely mastering and properly applying advanced EDA tools will become one of the necessary qualities.

At present, EDA covers a wide range of fields, including networks, communications, computers, aerospace, etc

. Products involve system board-level design, system digital/intermediate frequency analog/digital-analog hybrid/radio frequency simulation design, system IC/ASIC/FPGA design/simulation/verification, hardware and software co-design, etc. There are many manufacturers engaged in the research and development of EDA tools, the most representative of which are Cadence, Mentor Graphics, Synopsis, etc. Each manufacturer has its own strong products. From the perspective of market share, Cadence’s strong products are IC board design and services, Mentor Graphics’ strong products are PCB design and deep submicron IC design verification and testing, and Synopsis’s strong products are logic synthesis. It is difficult for any manufacturer to provide the strongest design process that meets various design needs. Manufacturers use product standardization to solve this problem, that is, allowing designers to use the strong products of multiple companies in their design process to form the best design process.

Concurrent design will be widely used

With the increasingly fierce competition in electronic products, it is very important to shorten the design cycle of products as much as possible and bring products to the market as soon as possible. The recently launched concurrent design method is an important way to shorten the design cycle of large electronic systems. Concurrent design is also called collaborative design, which is to divide a large circuit board into several parts and have several people design it at the same time. At present, some concurrent design tools can realize the docking and integration between the designs of each part, can “see” the designs of other designers, and can even realize completely real-time concurrent design. Mentor Graphics’ EDA tools have advantages in concurrent design. The full dynamic concurrent design tool ExtremePCB launched at the end of 2004 is more powerful and can realize completely real-time concurrent design. Cadence’s concurrent design tool will also be launched in the next version.

Conclusion

High speed and high density are one of the significant development trends of many electronic products. Research on high-speed and high-density PCB design technology has important practical significance. High-speed and high-density PCB design technology is very complex. It is restricted by the technical level of components, PCB boards, EMC, EDA, etc., and the related research work is being vigorously promoted. New materials, new processes, new products, and new technologies continue to emerge, making high-speed and high-density PCB design constantly face new problems, while also promoting the continuous development of high-speed and high-density PCB design technology. The discussion in this article has a guiding role in the research and application of high-speed and high-density PCB design technology.